DUV Immersion Lithography: The Foundation of the US AI Advantage

Executive summary

Advanced lithography systems are indispensable for producing competitive AI chips, but China is unlikely to commercialize these systems at scale until the mid-2030s. This gives the United States and its allies, the sole producers of these systems, extraordinary leverage over China’s AI ambitions.

Yet today Washington is giving away its leverage by permitting China to import deep ultraviolet immersion (DUVi) lithography systems capable of producing advanced AI chips. China has aggressively capitalized on this opening, amassing a large, growing stockpile of these systems as of early 2026. If Chinese DUVi imports continue at their 2024–2025 pace, China could accumulate enough lithography capacity over the next five to ten years to narrow or even erase the currently sizable US-allied advantage in AI chipmaking.

The United States can prevent this outcome with a simple policy change: replace the current, partial DUVi controls with a China-wide ban on all DUVi exports, with complementary controls on spare parts and servicing. This action would secure the US advanced AI chip production advantage (Figure 1)—and resulting AI capability advantage—for at least a decade and ensure that the next wave of advanced fabs is built in the United States and its allied countries, not China.

DUV immersion tools are the strongest chokepoint for limiting Chinese AI

Photolithography systems are the most important type of semiconductor manufacturing equipment (SME) for making advanced AI chips. Photolithography systems use ultraviolet light to print circuit patterns onto a silicon wafer, an essential step in the chipmaking process. The three most recent generations are dry deep ultraviolet (dry DUV), used since the 1990s; DUVi, introduced in 2006; and EUV, commercialized in 2019. Each successive generation can print finer circuit features, enabling production of increasingly advanced chips. ASML, a Dutch company, is the sole supplier of EUV systems and holds 99 percent of the DUVi market. Nikon, a Japanese company, holds the remaining 1% share of the DUVi market.^{Sidenote 1}

There is bipartisan support for limiting China’s indigenous chipmaking via controls on SME. The United States and its allies have restricted exports of SME to China since 2018. These controls tightened in 2019, when the Netherlands blocked shipments of ASML’s EUV systems, which are essential for producing the most advanced chips. Beginning in 2022, the US and its allies progressively expanded controls to cover DUVi systems and other critical types of SME. These controls have sharply constrained China’s AI chip production, allowing the US to accumulate an estimated 50× advantage in the production of AI computing power as of 2026.^{Sidenote 2}

Advanced photolithography (DUVi and EUV) systems are the most effective long-term chokepoint for limiting China’s AI chip production, for three reasons:

1. Advanced lithography is a prerequisite for manufacturing competitive AI chips. A chip’s capability depends on its “node”—a label (e.g., “7nm logic”) identifying a generation of chipmaking technologies used together in the manufacturing process. Competitive AI chips can only be made using advanced nodes and these nodes require DUVi or EUV. Chips made using nodes achievable with less advanced lithography (e.g., dry DUV)—28nm and above—are not competitive for AI.
2. China cannot currently make lithography tools capable of producing AI chips, and it is highly unlikely to do so at the scales needed to materially impact AI chipmaking before the mid-2030s. Its photolithography system manufacturers remain decades behind ASML and are unlikely to commercialize a DUVi capable of supporting the 7nm logic and advanced HBM used in Huawei’s AI chips before the early-to-mid 2030s.^{Sidenote 6} Additional years would be required to scale up production enough to materially expand AI chip output. China is even further behind in EUV, which it is unlikely to commercialize before the second half of the 2030s.
3. Advanced lithography is the hardest SME for China to develop. Chinese firms are rapidly closing the gap in other SME categories, such as etch and deposition, while making far slower progress in lithography. Advanced lithography will likely be the last chipmaking tool that China indigenizes.

Current export controls let China stockpile DUV immersion capable of producing Huawei’s AI chips

US, Dutch, and Japanese export controls allow China to acquire and maintain DUVi capable of producing Huawei’s AI chips. Controls ban EUV and ASML’s most advanced DUVi systems but leave three major openings for China to exploit:

1. ASML’s advanced DUVi systems, the NXT:1980i and NXT:1970i, are permitted to enter China despite enabling Huawei’s AI chips. The Netherlands requires a license for exporting these systems to any location in China, but public data shows that a large number of shipments are allowed. NXT:1980i supports making the pieces of silicon (called “dies”) (7nm logic and a form of advanced high-bandwidth memory called HBM2e) used in Huawei’s AI chips at high throughput.
2. ASML’s NXT:1965i and earlier DUVi are effectively uncontrolled. These systems can be exported anywhere in China without a license^{Sidenote 7} despite supporting 16/14nm logic and the less-advanced HBM2—nodes sufficient for earlier-generation AI chips.
3. Dutch servicing rules allow ASML to maintain China’s installed base of DUVi, including systems located at fabs making AI chips.^{Sidenote 8} Continued servicing and replacement components are necessary to keep these tools online in the long term.

Chinese fabs have aggressively capitalized on this opening, amassing a stockpile of over 330 DUVi systems by the first quarter of 2026, most of which are NXT:1980i systems (Figure 2). These systems can support China’s AI chip production through two pathways:

1. China may be able to directly obtain some NXT:1980i systems at fabs producing or capable of producing AI chips, rather than only at fabs capable of producing legacy chips. Available evidence suggests that CXMT, China’s leading producer of the high-bandwidth memory (HBM), a critical input for AI chips, has continued to acquire substantial numbers of DUVi systems in recent years. Hua Hong Semiconductor may likewise have stockpiled these tools for years as it prepared to launch a 7nm advanced logic production line.
2. Systems initially shipped to legacy fabs may later be repurposed to support AI chip production. China could divert entire systems or critical subsystems to advanced fabs (“physical diversion”), upgrade the original facility’s production node (“diversion in place”), or cycle partially processed wafers between fabs (“wafer diversion”).

Continued DUVi imports could eventually allow China to erase the US chipmaking advantage. China’s current DUVi stockpile is too small to match US chip production. However, if China were to maintain its 2024–2025 pace of NXT:1980i imports over the coming 5–10 years and fully mobilize the resulting fleet of DUVi for AI chip production, it could produce hundreds of millions of H100-equivalents^{Sidenote 9} each year—enough to approach or surpass US and allied output under some scenarios (Figure 1).

Banning DUV immersion to China would secure America’s long-term AI advantage

The US has all of the authorities needed to close the DUVi loophole. The following actions are necessary:^{Sidenote 10}

1. Ban all^{Sidenote 11} DUVi exports to China, including DUVi produced by ASML and Nikon outside of the United States. If Japan or the Netherlands is unwilling to do this using their own authorities, the US can do so unilaterally using the foreign direct product rule (FDPR),^{Sidenote 12} de minimis authority,^{Sidenote 13} or by controlling critical US-produced DUVi subsystems when the exporter has knowledge that the “end use” is incorporation into a DUVi system known to be destined to China.^{Sidenote 14}
2. Ban servicing of all DUVi at advanced-node Chinese fabs by foreign persons. The United States already prevents US toolmakers from performing any form of servicing at advanced fabs. However, the Netherlands permits its citizens to provide the minimum level of servicing needed to maintain China’s DUVi fleet. The US government can unilaterally ban servicing of DUVi located in an advanced-node fab using the Export Administration Regulations’ (EAR) General Prohibition 10.^{Sidenote 15}
3. Prevent diversion of China’s existing DUVi stockpile to AI chip production. ASML may have the technical capability to neutralize diversion.^{Sidenote 16} The US government should work with the Netherlands and ASML to assess this capability and ensure it is robust to countermeasures.
4. Restrict subcomponents, precursors, and knowledge transfers that enable China’s efforts to indigenize advanced DUVi or keep installed DUVi systems online. Priorities include Zeiss projection optics, rumored to be circulating within China, together with the materials and equipment (e.g., fused silica) needed to make comparable lenses; high-power ArF excimer light sources and their subcomponents and consumables; and precision wafer and reticle stages and their motion sensors. To mitigate impacts on legacy production, licenses could be granted for one-for-one replacements at verified legacy facilities.

These actions would have the following strategic effects:

1. A China-wide ban on DUVi exports would ensure the United States an overwhelming AI chipmaking advantage through at least 2035 (Figure 1). China’s existing DUVi fleet could not match US-allied output even if every system were redirected to AI chip production, but continued imports could erase this advantage. A China-wide ban would close this pathway and preserve the US advantage at least until China can commercialize domestic 7nm DUVi lithography—unlikely before the mid-2030s.
2. Tighter servicing controls would slow China’s near-term AI chipmaking ramp by degrading the performance of DUVi installed at China’s AI chipmaking fabs. A ban on new exports has a smaller immediate impact^{Sidenote 17} but may also degrade near-term production by preventing replacement DUVi systems and subsystems from reaching China’s advanced fabs.
3. New advanced chipmaking capacity would shift away from China and towards the US and its allies. Demand for advanced chips would not disappear if Chinese fabs can no longer expand; it would move to producers elsewhere. Allied memory manufacturers Micron, Kioxia, Samsung, and SK hynix would face less subsidized competition from China’s CXMT and YMTC. Logic foundries TSMC, Intel, and Samsung will absorb demand otherwise filled by SMIC. US and allied chip designers would also benefit. Existing controls already prevent them from manufacturing using Chinese advanced fabs, while Huawei faces no such limitation. Additional constraints on Chinese advanced capacity would therefore disproportionately affect Huawei.
4. Effects on China’s legacy production can be avoided. China could continue importing dry DUV systems, which are sufficient for all of China’s legacy logic and memory nodes. Some DUVi systems are installed in legacy fabs, but policymakers can choose to apply servicing restrictions only to fabs producing advanced chips, leaving legacy fabs untouched.^{Sidenote 18}
5. ASML would bear the primary cost among US and allied toolmakers, but the impact would be modest and mostly recoverable. ASML’s backlog of non-China orders is large enough to keep production lines occupied for months after a cutoff. In the longer term, new fabs built outside of China would create additional demand for ASML equipment. ASML’s former CEO, Peter Wennink, stated in 2022 that even if China were “excluded from any growth,” new fabs would be built elsewhere and ASML’s 2030 outlook would not change much. We estimate that the principal near-term loss is approximately $1–1.5 billion in annual Chinese servicing revenue, equivalent to 3–4 percent of ASML’s 2025 sales. Some of this near-term servicing loss could ultimately be recovered if tighter servicing controls degrade China’s DUVi fleet, shifting production—and equipment demand—to fabs elsewhere.

1. Lithography is a key input to chipmaking

Lithography is a critical step in semiconductor manufacturing, in which ultraviolet light is used to print circuit patterns onto a silicon wafer. Modern chips contain many layers of circuitry, built up through repeated manufacturing cycles. In a typical cycle (Figure 3), the wafer is coated with a light-sensitive material called a photoresist; ultraviolet light is projected through a patterned mask onto the resist (the lithography step); the exposed pattern is chemically developed^{Sidenote 19}; and that pattern is then transferred, or etched, into the underlying material. The lithography step is performed by a dedicated machine known as a lithography system, which projects ultraviolet light through the mask onto the wafer in ultra-high resolution.

Lithography technology has advanced through several major paradigms over the past 60 years, each enabling resolution of orders-of-magnitude smaller features. Early systems used mercury vapor lamps to print features below half a micron. In the mid-1990s, the industry introduced systems using deep ultraviolet (DUV) light generated by krypton-fluoride (KrF) excimer lasers. The three subsequent lithography paradigms support virtually all modern advanced chip manufacturing:

• Argon fluoride (ArF) systems, referred to in this report as dry DUV systems (though the label also applies to KrF systems), were introduced in the early 2000s and use 193nm light generated by argon-fluoride excimer lasers to print features down to ~57nm.
• Argon fluoride immersion (ArFi) systems, also known as DUV immersion (DUVi) systems, project ArF light through a thin layer of highly purified water,^{Sidenote 20} which enabled printing features down to ~38nm.
• Extreme ultraviolet (EUV) systems entered volume production in 2019, following decades of research and development, and use 13.5nm light to print features that would require prohibitively complex patterning with DUVi. These systems support today’s most advanced chips.

ASML, a Dutch company founded in 1984 overwhelmingly dominates the supply of advanced lithography systems. ASML is the sole supplier of EUV systems and accounts for approximately 99% of the DUVi market. Its main competitor in DUV lithography—and only remaining commercially viable competitor in DUVi—is Japan’s Nikon, while Canon, also of Japan, continues to supply older systems (e.g., i-line lithography tools).^{Sidenote 21} (China has reportedly begun small-batch production of domestic DUVi systems, as discussed in Section 3, but none has been shown to be production-worthy for advanced nodes.) Nearly all of ASML’s current DUV and EUV systems use its TWINSCAN architecture, a dual-stage design in which one wafer is measured and aligned while another is exposed, improving throughput and overlay. ASML markets two major TWINSCAN DUV platforms: the XT series, used for KrF, dry ArF, and early ArFi (i.e. DUVi), and the NXT series, used for later ArFi and which provides higher overlay precision and throughput. ASML’s EUV systems are divided into two series as well: NXE systems use conventional numerical aperture EUV, while the newer EXE series uses high numerical-aperture (high-NA) optics to further improve resolution^{Sidenote 22} and is entering volume production in 2026. Several notable ASML systems are enumerated in Table 2:

2. DUVi is needed for competitive AI chips

Modern AI chips incorporate two kinds of silicon: (1) logic dies, used to perform computations, and (2) dynamic random access memory (DRAM) dies, used to store data. Both dies use advanced “nodes”—i.e., successive generations of semiconductor manufacturing technology, labeled in nanometers (e.g., “7nm” logic). Competitive AI chips use logic nodes at 16/14nm and below and DRAM nodes at 20nm or below. These nodes cannot realistically be implemented without DUVi or more advanced (EUV) photolithography, because older (dry DUV) lithography systems lack the resolution and overlay performance needed to reliably pattern their small, tightly spaced features. Falling back to older process nodes sharply reduces chip performance and power efficiency, making such chips uncompetitive for frontier-scale AI. Access to DUVi systems is therefore a prerequisite for competitive AI chipmaking.

Modern AI chips are made using process nodes that require DUVi

Modern AI chips incorporate two kinds of silicon. The first is one or more logic dies, processors specialized for performing computations used for AI. The second is high-bandwidth memory (HBM), a specialized form of vertically stacked DRAM that stores model parameters and other data and is designed to move that data to and from the logic dies at high speeds.

Both types of silicon are manufactured using advanced nodes. A process “node” is a label^{Sidenote 23} (e.g., 7nm logic, 1x DRAM) identifying a generation of semiconductor manufacturing technologies. Each successive node combines advances in lithography and complementary manufacturing technologies—including deposition, etch, and metrology—that together enable smaller and more densely packed circuit features, thus improving chip performance and power efficiency. For logic chips, advanced nodes increase transistor density,^{Sidenote 24} allowing designers to pack more computational units, wider data paths, and larger caches into each unit of silicon area, while also improving the performance and power-efficiency of individual transistors. This enables processors with better computational performance and power efficiency. For DRAM, advanced nodes increase bit density,^{Sidenote 25} enabling more memory to fit on each chip, reducing cost per bit, and improving power efficiency per bit. This enables HBM with better capacity, bandwidth, and power efficiency.

NVIDIA’s major AI chips over the past decade reflect this pattern. All have combined logic processors manufactured using 16/14nm or more advanced nodes with HBM manufactured using 20nm or more advanced DRAM (Table 3):

Which process nodes a fab can implement depends in part on the capabilities of its available lithography systems. Three capabilities of a lithography system are especially important in determining which process nodes it can implement in a semiconductor fab setting: minimum resolvable feature size (MRF), overlay, and throughput. “Minimum resolvable feature size” (MRF) determines the smallest feature that can be printed in a single exposure—i.e., a dose of light that transfers a pattern onto the wafer. MRF is typically expressed in terms of “half pitch”—i.e., half the distance from the center of one line to the center of the next in a repeating line-and-space pattern, or roughly the width of one line. “Overlay” measures the alignment error between a newly printed pattern and the underlying patterns on the wafer.^{Sidenote 29} “Throughput” measures the rate at which the system can expose wafers. A lithography system is viable for a given process node only if it can meet the node’s patterning requirements at acceptable yield and cost. It must print the node’s smallest features, either in a single exposure or through multi-patterning—i.e., techniques that split a single layer’s pattern across multiple exposures or other patterning steps; align successive patterns precisely enough to avoid defects and degraded electrical performance; and do so fast enough to sustain economical high-volume production.

The process nodes used for modern AI chips require DUVi or more advanced lithography. For logic, all major foundries adopted DUVi at least five years and two nodes before introducing the 16/14nm node.^{Sidenote 30} Compared with dry DUV and earlier lithography, DUVi provides two advantages that make advanced nodes viable:

• Better single-exposure patterning capability. DUVi systems can resolve patterns with roughly 38nm half-pitch in a single exposure, compared with roughly 57nm for dry DUV. Aggressive multipatterning—particularly self-aligned quadruple patterning—could in principle be used to allow dry DUV to pattern simple features (e.g., dense arrays of straight, regularly spaced lines) at advanced nodes. However, actual logic designs require irregular features (e.g., line ends, cuts, contacts, corners) that cannot be easily split across exposures. Patterning advanced-node chips using dry DUV’s resolution would therefore impose extremely restrictive design rules, reducing effective transistor and interconnect density and potentially precluding the layouts needed for high-performance logic. Even if such a design could be developed (no attempt has been made), the multipatterning would greatly increase process complexity, worsen unit economics, and reduce yield because of increasing opportunities for alignment errors.^{Sidenote 31}
• Better alignment between layers. All existing dry DUV systems, including ASML’s most advanced NXT:1470, have far worse overlay performance than DUVi systems. Poorer overlay leaves less margin for aligning patterns between layers or within a single layer (assuming multipatterning is used), increasing alignment errors and lowering yields. With a focused effort, ASML might be able to improve the overlay of dry systems, but even then the disadvantages due to worse resolution would remain.

See Appendix C for further analysis of dry DUV’s insufficiency at advanced logic nodes. For DRAM, industry transitioned to DUVi around 2008–2010, several years and multiple shrinks before 20nm-class DRAM entered high-volume manufacturing.^{Sidenote 32} Although DRAM’s regular arrays are relatively amenable to multipatterning, a complete DRAM process must also pattern irregular features in the periphery. There is no demonstrated dry DUV process for manufacturing 10nm-class DRAM (including the nodes used for HBM2e and more advanced HBM) and the prospect of one being developed (in China or elsewhere) appears extremely unlikely because of these technical and economic constraints.

Less advanced nodes cannot support competitive AI chips

AI chips made on nodes that can be implemented using earlier lithography technologies (e.g., dry DUV) are not competitive with chips made using advanced nodes. Matching the processing performance and memory bandwidth of NVIDIA’s B100 AI chip using nodes that can be implemented without DUVi (28nm logic and HBM1) would require ~9.6× as much logic silicon area, 5× as much DRAM silicon area, and ~4.4× as much chip power (Figure 4). See Appendix A for assumptions and calculations.

These technical limitations substantially impede frontier AI training and inference. First, less advanced nodes require far more chips to deliver the same processing power and memory bandwidth. Accommodating these additional chips requires a much larger cluster and datacenter, increasing capex not only for chips but also for packages, boards, networking equipment, power-delivery and cooling equipment, cabling, and other supporting hardware. Second, chips made at less advanced nodes are much less power-efficient, requiring more electricity to enable the same processing throughput. This raises operating costs, increases the amount of power that must be obtained from the grid or from on-site generation, and necessitates more on-site power distribution and cooling infrastructure. Third, distributing workloads across many more chips substantially reduces FLOP/s utilization (i.e., the share of theoretical processing capacity that is productively used for training or inference), because more time is spent moving data and coordinating work across devices. This lengthens training runs, reduces inference throughput and user-facing responsiveness, and further increases operating costs. Finally, the complexity of managing the cluster increases^{Sidenote 33} at least linearly, and potentially superlinearly,^{Sidenote 34} with its size, requiring far more engineering investment.

A back-of-the-envelope comparison illustrates the impact of these disadvantages (Figure 5). At full buildout, OpenAI and Oracle’s Stargate Abilene supercluster is expected to contain >450,000 NVIDIA GB200 GPUs and draw ~1.2 GW of power across ~4 million square feet of datacenter space. Replicating a cluster of this scale using nodes achievable without DUVi would require ~4.3 million packaged chips, assuming our 9.6× logic silicon scaling factor translates proportionally into package count. It would also require correspondingly more CPUs, boards, networking switches, cabling, cooling systems, power delivery systems, and other supporting hardware. For power, a 4.4× penalty implies ~2.4 GW consumed by logic chips and co-packaged memory. Assuming 100% overhead for CPUs, networking, cooling, and other infrastructure, total datacenter power demand would reach ~4.8 GW—roughly the output of five large nuclear reactors. Assuming datacenter and campus area scales proportionally with chip count, the cluster would require ~38 million square feet of datacenter space. These estimates are illustrative, given that industry has never contemplated building a cluster of this scale using legacy nodes, and an actual design would likely make different engineering tradeoffs.

The relative disadvantage of 28nm nodes will only get worse over time. NVIDIA’s Rubin AI chips, releasing in the second half of 2026, use TSMC’s more advanced 3nm node, and leading chipmakers are now commercializing production of next-generation 2nm nodes.

3. DUVi is the top chokepoint for China’s AI chipmaking

DUVi and more advanced lithography systems are the hardest SME to develop. No other category of SME requires comparable R&D investment, development time, or supply chain complexity. As a result, China remains far behind the ASML-led ecosystem and is highly unlikely to produce DUVi systems at a scale that materially expands its AI chip production until the mid 2030s.

Advanced lithography is the hardest SME to indigenize

Advanced lithography is exceptionally difficult to develop, for two interrelated reasons. First, a lithography maker must develop dozens of highly specialized subsystems to an extremely high standard of precision and reliability. Second, these subsystems must be seamlessly integrated to function as a single, high-performance machine, which requires overcoming an additional set of steep engineering challenges. We review these challenges in Appendix B.

The extreme difficulty of developing advanced lithography is reflected in several aspects of the industry’s history and present-day structure. First, new lithography technologies have historically taken decades to mature. ASML’s TWINSCAN platform—the foundation of modern DUVi systems—has been under continuous development for about 25 years, while EUV took over 30 years between initial conception and commercial adoption. As one ASML engineer informed a competitor’s CEO, even possessing full technical blueprints would not be enough to reproduce ASML’s systems, because they embody “decades, if not centuries” of accumulated tacit knowledge.

Second, even established lithography companies with decades of optical engineering expertise have struggled to execute technological transitions. The shift from dry to immersion DUV effectively pushed Canon out of the market; it never achieved commercially viable production. Nikon was able to commercialize immersion systems but lost substantial market share. Both Nikon and Canon abandoned their EUV programs entirely. The result is an extraordinarily concentrated market: ASML accounts for 99% of DUVi sales, with Nikon accounting for the remaining sliver.

Third, remaining at the technological frontier requires larger R&D investments than in any other SME category. ASML’s annual R&D expenditure on lithography exceeds $5.3 billion—more than the total company-wide R&D budgets of diversified equipment makers like Applied Materials (~$3.6 billion) or Lam Research (~$2.1 billion), which are spread across many equipment categories.^{Sidenote 35} ASML has invested tens of billions of dollars in R&D since its founding in 1984. EUV alone required ~$14–21 billion of total industry investment across ASML, national laboratories, suppliers, and other partners.

Fourth, lithography tools are far more valuable than—and therefore likely more complex than—other SME. A state-of-the-art DUVi system is worth $80–100 million, far more than the most advanced systems in other categories (Figure 6). By contrast, a typical etch or deposition chamber costs just $1–3 million.

China is highly unlikely to produce DUVi at a scale that materially expands its AI chipmaking until the mid-2030s

Our central estimate is that China will develop commercially viable DUVi capable of 7nm production in the mid-2030s, though commercialization in the early 2030s is plausible. However, commercial viability is only the first milestone. Even if 7nm DUVi were to be commercialized in the early 2030s, scaling up production enough to materially increase AI chip output beyond the levels supported by China’s existing DUVi stockpile (Section 6) would require several additional years. China’s indigenous DUVi will likely not achieve that milestone before the mid-2030s.

Extrapolations based on ASML’s product development timelines and China’s historical lag in lithography capabilities both imply commercialization of 7nm-capable lithography in the mid-2030s. China’s lithography prototypes have historically reached user-testing milestones 13–19 years after roughly comparable process nodes entered volume production outside China. For example, SMEE’s SSB600/10 i-line scanner, which targets 280nm production, was shipped to a customer for testing in 2016,^{Sidenote 36} roughly 19 years after 250nm entered high-volume manufacturing. SMEE’s SSA600/20 passed expert on-site testing in October 2017,^{Sidenote 37} roughly 13 years after TSMC began 90nm volume production. Most recently, the Financial Times reported in September 2025 that SMIC had begun testing a 28nm DUVi system from Shanghai Yuliangsheng, 14 years after TSMC’s introduction of 28nm; follow-on reporting in 2026 indicated that the tool had entered low-volume production.^{Sidenote 38} Extrapolating this 14-year lag beyond TSMC’s introduction of 7nm in 2018 implies the arrival of a prototype for 7nm production in 2032.

ASML’s product-development history supports a similar timeline. Nearly seven years elapsed between ASML’s first shipment of NXT:1950i in early 2009 and first shipment of 7nm-capable NXT:1980i in late 2015. Extrapolating this development interval beyond China’s 2025 prototype, which was described as comparable to NXT:1950i also points to 2032 for a 7nm-capable prototype.

Productizing a 7nm-capable prototype to support high-volume manufacturing (HVM) would likely require at least another 1–2 years of qualification. For example, ASML’s NXT:2000i took two years between initial announcement and HVM ramp,^{Sidenote 39} while NXT:1980i^{Sidenote 40} took about 13–15 months and NXT:1950i at least a year and a half.^{Sidenote 41} Together, these factors put our central estimate for the first commercially viable Chinese 7nm-capable DUVi in the mid-2030s (Figure 7). This conclusion also aligns with the historical base rates estimated by the AI Futures Project, which indicate 2032–2038 for commercial-scale 7nm-capable Chinese DUV.^{Sidenote 42}

Several factors might allow China to progress faster than ASML did in the past. Perhaps most importantly, China is not starting from a blank slate. Chinese firms can learn from published research and patents, study the architecture of existing ASML tools, poach former ASML engineers, and draw on China’s huge installed base of DUVi systems. For example, Reuters reported in 2025 that China had recruited former ASML engineers for a secret EUV project and was reverse engineering subsystems from DUV and EUV tools, using a dismantled system. Although physical access cannot transfer all of ASML’s accumulated manufacturing and systems-integration knowledge, it can reveal component designs, interfaces, tolerances, and architectural choices, reducing the space of unknowns that must be investigated.

China is also committing large amounts of capital towards acquiring advanced lithography capabilities. The Big Fund III, which began operations at the end of 2024, has $47 billion in registered capital, with equipment makers among its principal targets.^{Sidenote 43} In parallel, Huawei is building or supporting multiple fabs and investing across the lithography supply chain. Its involvement could help coordinate component suppliers, lithography subsystem developers, and chip manufacturers, accelerating the development of building an integrated supply chain.

There is also an outside chance that China can bypass parts of ASML’s optical-development pathway. Researchers are exploring alternative paths towards advanced lithography, including free-electron lasers for EUV and entirely different approaches like X-ray lithography. The most significant Chinese effort is a Tsinghua University program that uses steady-state microbunching (SSMB) to generate EUV light. That said, these alternative approaches remain at an early experimental stage and have not been demonstrated even in a prototype.

On the other hand, there are also reasons to expect that China’s progress will be slower than ASML’s. First, China’s lithography makers have an extremely poor track record of commercializing their prototype systems, particularly due to gaps in accumulated implicit process knowledge. China’s lithography makers have zero market share in either of the two DUV technology generations (dry ArF and dry KrF) preceding DUVi systems, with no increase from 2019 to 2025. For example, Shanghai Micro Electronics Equipment (SMEE) released tests of a prototype dry ArF 90nm tool (SSA600/10) in 2011; roughly 13 years later, neither that tool nor its successor, the SSA600/20, appeared to have achieved meaningful domestic sales or production-readiness. Even in the ultra-legacy i-line segment, China achieved only a minimal (4%) market share by 2025 and remains unable to satisfy its own domestic demand. For example, Nikon relaunched its legacy NSR-2205iL1 i-line stepper in 2024 specifically to meet unmet Chinese demand. External analysts and members of China’s industry consistently express deep skepticism about the production-readiness of domestic systems. In 2023, a Chinese semiconductor executive stated: “Homegrown lithography was examined and verified by academics, not industrial engineers. This equipment is only theoretically usable, and no chip manufacturer has ever dared to activate such a machine in their fabs.” This matches views expressed by external analysts, for example: “Nothing has ever come of these reports in terms of equipment in mass production fabs. Instead, SMEE has created demonstration equipment in its laboratory.” Commenting on social media in 2024, a semiconductor industry veteran expressed the view that “even if we mobilize the whole nation and everything goes well, it is only in six years—around 2030—that we might have a chance to produce 28nm chips using fully domestic [immersion lithography] systems.” Commenting in 2026, a Chinese analyst stated: “Lithography is the biggest foreign dependency; the domestic share isn’t even 5%. SMEE’s 28nm DUV is still under development; the lithography link has no near-term solution.”

Second, China’s supplier ecosystem is less mature than ASML’s, both in absolute terms and also relative to the capabilities of its DUVi prototypes. For example, Yuliangsheng’s 28nm prototype tool reportedly uses a legacy ArF excimer laser from Keyi Hongyuan. The laser’s technical specs (6 kHz / 60W) are comparable to XLR 500i, which Cymer—which supplies light sources for and is now a division of ASML—introduced for the less advanced 45nm node in 2007. For photoresists, Chinese KrF resist suppliers meet only 5 percent of domestic demand and the country remains almost entirely dependent on Japanese suppliers for ArF resists (including ArF immersion and even earlier-generation products for dry ArF). For projection optics, China’s key suppliers (Changchun UP Optotech, Nanjing Wavelength, Beijing GuoWang Optics) themselves depend heavily on foreign suppliers for critical subcomponents.

Third, China’s funding model may struggle to cultivate the highly specialized supply chains and coordination mechanisms that have enabled the success of ASML’s ecosystem. For years, China funded SME development, including lithography, through the 02 Special Project, a state megaproject launched in 2008. This state-backed R&D model succeeded at fostering research breakthroughs and working prototypes but was poorly suited to translating them into commercially viable systems—particularly for lithography, which requires highly specialized supply chains, developed over time through market evolution, and extremely tight iterative feedback loops between integrators, subsystem suppliers, and fabs.

Huawei’s recent involvement may partly correct this weakness. But Huawei remains a new entrant in the space, with less experience orchestrating the SME supply chain compared to ASML. The underlying difficulty is that indigenizing commercially viable DUVi is neither the kind of commodity manufacturing at which China’s subsidy-based funding model excels, nor a pure research challenge that can be solved through laboratory investment alone. In the words of one Chinese commentator, the fundamental problem in developing a “new-type national system [for directing national resources towards the development of strategic technologies] is coordinating it with market forces.” Where China has achieved relatively greater success in its SME industry, such as with AMEC’s and Naura’s development of etch and deposition tools, it did so by developing a competitive, commercial industry—unlike SMEE’s unsuccessful lithography efforts, which relied on state-backed R&D.

Finally, even if China commercializes a 7nm-capable system in the early 2030s, scaling production and adoption to a level that materially expands overall chipmaking capacity would take several additional years. Initial production is likely to be small: for example, Shanghai Aishengna reportedly plans five systems in 2026 and 20 in 2027. Rapid growth thereafter would be difficult to sustain. A CSET review estimated 60% as the highest historical rate of growth across the lithography industry, achieved first at Nikon and later at ASML. China already has more than 300 imported DUVi systems in-country (Section 6). Although only a subset of these support AI production, an initial batch of domestic scanners would add little to that capacity. To materially expand output, China would need to produce high tens of commercially-viable systems annually, which would take several additional years. An impact at that scale before the mid-2030s is unlikely.

4. SME export controls have granted the US a strong lead in AI chipmaking

The United States and its allies have restricted SME exports to China since 2018, when the US government put China’s then-memory chipmaking champion Fujian Jinhua on its export blacklist, the Entity List, effectively cutting it off from US-origin SME. These controls tightened in 2019, when the Netherlands first withheld authorization for ASML to ship extreme ultraviolet lithography (EUV) systems to China, and again in December 2020, when the United States added China’s leading logic foundry, SMIC, to the Entity List. The Biden administration then expanded these measures through a series of rules issued in October 2022, October 2023, December 2024, and January 2025, implemented alongside parallel controls adopted by key allies Japan and the Netherlands.

The current SME control framework is designed to restrain China’s production of advanced semiconductors without unduly restricting its ability to produce legacy semiconductors.^{Sidenote 44} The US government defines three categories of “advanced-node” chip production: (1) logic chips using a non-planar transistor architecture or produced at or below the 16/14nm node, (2) NAND flash with 128 layers or more, and (3) DRAM meeting specified thresholds for cell area, memory density, or through-silicon-via density.^{Sidenote 45} Using these thresholds, the United States implements two types of controls on SME, described below and visualized in Figure 8.

First, the US imposes China-wide controls on the most advanced tools,^{Sidenote 46} including EUV, the most advanced DUVi systems, and advanced etch, deposition, and metrology equipment. These tools are considered to be particularly important chokepoint tools used only for advanced production, justifying a control scope applying throughout China. The US also extends these restrictions to foreign-made equipment using a legal authority called the SME foreign-produced direct product rule (FDPR), but exempts qualifying exports and reexports by eligible entities located in 33 allied countries. These include Japan and the Netherlands, both major producers of many of these tools, which have enacted their own parallel, China-wide controls. The combined effect of these overlapping controls is to block exports of any of these tools to China, regardless of their country of origin.

Second, the US additionally controls a broader set of items when they are destined to specific restricted entities within China. For any item subject to US jurisdiction,^{Sidenote 47} exports are restricted whenever there is knowledge that the item will be used in “development” or “production” of ICs destined to a facility where “advanced-node” production occurs or to any entity on the Bureau of Industry and Security (BIS) Entity List. Twenty-one Chinese chipmaking entities are on the Entity List.^{Sidenote 48} For certain Category 3 items subject to US jurisdiction, restrictions also apply when the exporter knows the destination is an IC fab but does not know whether advanced-node production occurs there. Practically, these restrictions prevent US toolmakers from providing SME, components, software, or technology to any of China’s advanced fabs, including SMIC and CXMT.

The US uses the Footnote 5 FDPR to extraterritorially control an enumerated list of foreign-made tools^{Sidenote 49} when destined to specific restricted entities—16 of the 21 on the Entity List. This set of tools is considered to be “node-agnostic”—i.e., important for advanced production but also required for legacy production, making a China-wide control detrimental to legacy production—and includes advanced DUVi systems^{Sidenote 50} and etch, deposition, and metrology equipment. Covered foreign-made equipment requires a BIS license when it is destined for a Footnote 5 entity on the BIS Entity List or a facility where “advanced-node integrated circuit” production occurs.

Japan and the Netherlands are exempted from the Footnote 5 FDPR but implement their own parallel controls on a similar set of technologies.^{Sidenote 51} For example, the Netherlands’ 3B801 controls DUVi systems with dedicated chuck overlay (DCO) at or below 2.4nm, matching US Export Control Classification Number (ECCN) 3B993.f.1.b.2. However, there are two key differences. First, unlike the US, Japan and the Netherlands do not employ a mechanism to impose controls on specific entities. Instead, all of their controls on SME are nationwide, with the ability to grant licenses for shipments to specific entities on a case-by-case basis. The license review policy used to determine which entities may receive controlled SME is not public, but there is ample public evidence that both countries approve sufficient licenses to enable a huge volume of shipments into China. Second, Japan and the Netherlands control only a specific set of tools (a subset of the tools covered by the Footnote 5 FDPR), leaving less advanced SME—including earlier DUVi systems—uncontrolled (see below).

The US and its allies also restrict servicing of SME. Servicing activities are vital for ensuring continuous operation of advanced SME. For a lithography system, these activities can include on-site installation, calibration and qualification, preventative maintenance, corrective repair, remote troubleshooting, and field upgrades. US rules define covered servicing to include “maintaining, repairing, overhauling, or refurbishing” and require a license whenever a covered US person services certain items involved in “development” or “production” of “advanced-node ICs,” with an exclusion for persons working for qualifying US or allied-headquartered companies. Practically, this prevents US persons from performing any servicing in China’s advanced fabs.

The Netherlands takes a narrower approach to servicing controls. Unlike the US rules, Dutch controls do not generally prohibit a Dutch person from performing servicing simply because it occurs at an advanced-node facility. Instead, restrictions apply only to transfers of certain software and technology associated with specifically controlled equipment. Dutch rules cover transfers of “technology” or “software” “required” for the “development,” “production,” or “use” of the tool. Because “use” encompasses activities such as operation, installation, maintenance, and repair, these provisions can in principle prohibit activities typically involved in routine servicing. However, Dutch controls also exempt transfers of the minimum necessary technology to support installation, operation, maintenance, or repair, for legally exported items, such as DUVi systems exported to and installed in China.^{Sidenote 52} In practice, these exceptions allow ASML to continue to service DUVi systems exported under a Dutch license, provided the servicing does not transfer technology and software beyond what is minimally necessary.

Finally, Japan takes arguably an even narrower approach than the Netherlands. For controlled SME only, Japan controls transfers of software programs that support design, manufacturing, or use, where use encompasses operation, installation, maintenance/checking, repair, overhaul, and disassembly repair. By contrast, non-software technology is controlled only when “related to design or manufacturing.” Thus, Japanese technicians can provide non-software technical information or know-how, including nearly all ordinary hands-on maintenance, so long as the know-how does not facilitate designing or manufacturing the equipment.

Export controls on SME have provided the US and its allies with a large advantage in AI chip production over China. Controls constrain production of both kinds of silicon used in China’s AI chips: advanced logic at 7nm and below, produced primarily at SMIC, and HBM, produced primarily at CXMT. In both cases, controls have limited the volume of advanced equipment available to build and expand advanced production lines and reduced yields on the lines that can be implemented, as fabs are forced to push less capable equipment beyond its normal process envelope while operating without access to servicing support. At SMIC, limited access to advanced deposition, etch, and DUVi systems has constrained expansion of 7nm capacity used for Huawei’s Ascend chips and reduced yields, which were reported as “weak” as recently as spring 2026. At CXMT, the same combination of equipment scarcity and low yields, estimated at only 25% for HBM3 as of June 2026, has constrained its HBM2 and HBM3 capacity ramp, likely making HBM the binding constraint on HBM-based AI chip production as of 2026—though Huawei also now markets the non-HBM-based Ascend 950PR which is instead constrained by China’s 7nm logic wafer capacity. Together, these constraints have limited China’s AI chip production to only a small fraction of the US-led ecosystem’s production. In an Institute for Progress report, one of this report’s authors (Khan) and colleagues compiled estimates placing Huawei’s production between 40,000 and 146,000 B300-equivalent chips (normalized by total processing performance) in 2025, compared with 3.67 million for US firms, and 62,000–160,000 in 2026, compared with 6.89 million for US firms (Figure 9).

5. Export controls let China import DUVi capable of mass-producing Huawei AI chips

Controls on lithography system exports vary depending on the technology generation, national jurisdiction, and facility within China. The most advanced systems—including EUV and the most advanced DUVi—are banned anywhere in China. Advanced DUVi systems—including ASML’s NXT:1970i and NXT:1980i—may be shipped into China but are banned to Entity-listed fabs and fabs that engage in “advanced-node production”, when US controls apply. Under Dutch or Japanese controls, these systems require a license for shipment anywhere in China, but ample public evidence suggests that many shipments are allowed. The least advanced systems—including ASML’s NXT:1965i and earlier DUVi systems, dry ArF and KrF systems, and older lithography technologies—are banned to Entity-listed or “advanced-node” fabs when US controls apply but permitted anywhere in China by Japanese and Dutch controls.

Controls on servicing vary similarly based on technology, jurisdiction, and destination. US toolmakers are banned from performing any servicing activities within “advanced-node” or Entity-listed fabs and on any system exported in violation of the EAR, which de facto restricts them from servicing NXT:2000i or more advanced systems, China-wide. Japan’s and the Netherlands’ servicing controls apply to systems rather than persons. For systems at or more advanced than NXT:1970i, the Netherlands controls transfers of “technology” or “software” for the “use” of the system, but with a general exemption for servicing support required to ensure its continued operation; less advanced systems can be serviced wherever located. Japan restricts transfers of “software” for the “use” of the system but only “technology” transfers when they facilitate design or manufacturing. See Table 4:

US controls on the most and least advanced lithography systems reflect a policy objective to restrain China’s advanced production without affecting legacy production. The most advanced DUVi systems, which benefit nodes at 5nm and below^{Sidenote 54} but have substitutes at all legacy nodes, are banned China-wide, minimizing the risk of diversion. At the other end of the spectrum, legacy systems (e.g., dry DUV and i-line lithography), which cannot support advanced logic or memory nodes but remain essential to legacy production, are permitted China-wide.

However, controls on advanced DUVi systems (ASML’s NXT:1980i, NXT:1970i, and less capable predecessors) undermine this policy objective, in three ways. First, ASML’s NXT:1980i can support the logic (7nm) and memory (1y) production nodes used for Huawei’s Ascend AI chips, yet is allowed into China.^{Sidenote 55} Second, less advanced DUVi systems (e.g. ASML’s NXT:1965i and predecessors) are permitted to enter China’s advanced fabs, despite supporting 14nm logic and 1x memory, nodes used to produce earlier-generation AI chips such as Groq LPUs and the NVIDIA V100. Third, Dutch servicing controls permit ASML technicians to support continued operation of DUVi anywhere in China, including at the most advanced fabs, allowing China to sustain its installed base indefinitely.

Problem #1: ASML’s NXT:1980i is allowed into China despite enabling production of Ascend AI chips at massive scales

NXT:1980i is an extremely capable lithography system that enables high-volume production of AI chips like Huawei’s Ascend 910C. For logic, the industry record unambiguously confirms that NXT:1980i can support the 7nm node used for the logic dies used in Huawei’s AI chips. ASML’s original technical paper introduced NXT:1980i as a “scanner for 7nm and 5nm production nodes.” TSMC later used the NXT:1980i to develop its first 7nm production line and said that the ramp set company records for “defect density reduction and production volume ramp rate.” Our own yield modeling (Appendix C) estimates that NXT:1980i can achieve 50–65% defect-free yield for a large (500mm²) 7nm die, with overall yield approaching 70–80% after accounting for redundancy (i.e. excluding defects that do not affect chip capability due to redundant circuits) and binning (i.e. chips that achieve lower performance than defect-free versions but are still marketable). These yields are only modestly below those achievable with state-of-the-art (EUV) lithography and would not materially constrain China’s logic production. Furthermore, Chinese fabs can also leverage roughly 28 (NXT:2050i/NXT:2100i) systems stockpiled over 2021–2023 (Appendix E) for the one or two most challenging layers in complex designs and NXT:1980i for all other immersion layers, greatly improving yields.

For memory, NXT:1980i can support the 1x and 1y nodes used for HBM2 and HBM2e.^{Sidenote 56} ASML’s technical writeup introducing the NXT:1980i indicates it was designed with 1x memory as a target application. Public evidence also indicates support for 1y. ASML’s 2018 roadmap shows support for 1y a full year before NXT:2000i shipped, implying that early 1y ramps used NXT:1980i. Samsung’s initial 1y DRAM mass production in late 2017 was almost certainly implemented primarily using the NXT:1980i, since the successor NXT:2000i had only just begun limited early access testing at that point and did not begin shipping widely until 2018. Samsung claimed a “30 percent productivity gain” for DDR4 based on this 1y node.

NXT:1980i systems produce AI chips at massive scales. We estimate (Appendix D) that a single system operating in a state-of-the-art fab can produce 30,000–47,000 Ascend 910C-equivalents every month—or nearly half a million chips per year (Figure 11).^{Sidenote 57} China’s fabs achieve substantially lower yields than world-leading fabs, lowering effective throughput. Even so, we estimate a single NXT:1980i deployed in a Chinese fab with sufficient complementary SME could likely produce over 100,000 Ascend 910C-equivalents per year.

Despite this capability, NXT:1980i is allowed into China. The Netherlands requires a China-wide license for NXT:1980i, but public data confirms that many exports are allowed. The Dutch government has not disclosed the criteria it uses to determine which Chinese fabs can receive NXT:1980i. However, China’s customs import data (Appendix E) suggests the country is growing its installed base, including at advanced fabs. Even if licenses are consistently denied to certain fabs of concern, there is a serious risk that they may be illicitly diverted or otherwise leveraged to advance China’s AI chip production once physically in-country (Section 6).

Problem #2: Less advanced DUV immersion tools are uncontrolled despite enabling earlier AI chips

Older DUVi systems—including ASML’s NXT:1965i, 1950i, and XT:1900i—fall outside the scope of the Netherlands’ China-wide license requirement. The US restricts transfers of these older systems to advanced-node fabs but carves out the Netherlands from its FDPR; as a result, these tools are effectively uncontrolled anywhere in China.

The most capable of these systems (NXT:1965i and NXT:1950i) almost certainly enable the advanced logic (16/14nm) and memory (1x) nodes used for earlier AI chips like Groq LPUs. For logic, ASML explicitly markets NXT:1965i as a solution for “sub 20nm nodes,” implying viability for 16/14nm production. TSMC almost certainly ramped its 16/14nm node to risk production (i.e. a step before volume commercial production) using 1965i or earlier lithography systems, given that ASML’s NXT:1970i first shipped just one month before that milestone. For memory, the NXT:1965i appears to enable 1x production.^{Sidenote 58}

ASML does not currently sell NXT:1965i or older systems, but a thriving secondary market is available for these systems,^{Sidenote 59} within which China is reported to be a major participant. Recent industry rumors also claimed that ASML was considering restarting production of these systems specifically to support Chinese customers.

Problem #3: Dutch servicing rules preserve ASML’s ability to support China’s installed DUV immersion fleet

For controlled DUVi—NXT:1970i and more advanced systems—Dutch rules control transfers of “technology” or “software” “required” for the “development,” “production,” or “use” of the tool. Here, “technology” refers to controlled technical information, like engineering know-how and servicing instructions. “Use” includes operation, installation, maintenance, repair, overhaul, and refurbishing. By default, these provisions would substantially control the support that ASML can provide to China’s fabs.

However, Dutch controls also contain an exception that allows transfers of the minimum “technology” needed to install, operate, maintain, or repair^{Sidenote 60} an item if either the tool is uncontrolled or its export was authorized.^{Sidenote 61} A large fraction of controlled DUVi systems now in China were exported under Dutch licenses. This exception therefore ensures that ASML can continue to provide support needed to maintain most of China’s controlled DUVi fleet.

6. China is building a massive stockpile of DUVi that enable AI chipmaking

Chinese chipmakers are importing vast numbers of DUVi systems, the large majority of which are NXT:1980i capable of making Ascend AI chips. China first began importing NXT:1980i systems in the late 2010s, after the tool first entered commercial production, but drastically accelerated imports after the Dutch government announced export controls on more advanced DUVi systems in 2023 (Figure 2). As of 2026Q1, we estimate that roughly 270 NXT:1980i systems are installed in Chinese-owned fabs,^{Sidenote 62} accounting for ~80% of the advanced DUVi stockpile at these entities. The remainder of China’s DUVi stockpile consists of an estimated 22 NXT:2050i systems, imported between 2021 and 2023 before China-wide restrictions took effect in January 2024; 6 NXT:2100i systems, imported over the same period; and ~45 DUVi systems less advanced than the NXT:1980i. See Appendix E for our estimation methodology.

China’s surge of NXT:1980i imports has absorbed a large fraction of ASML’s system sales and required a massive investment from China’s chipmaking industry. Within the DUVi segment, China’s share of ASML shipments surged from 26% in 2022 to 60–70% over 2024Q1–2026Q1. We estimate that China spent over $13 billion on NXT:1980i systems over 2024–2025 alone.

China’s NXT:1980i imports risk advancing its AI chip production

China’s continued imports of NXT:1980i systems could support AI chip production through two pathways. First, systems delivered to China’s advanced fabs can directly advance their capacity to produce AI chips. Although the Dutch government requires licenses for all NXT:1980i exports to China, it does not publicly disclose the criteria used to review individual license applications. It is therefore unclear whether the Netherlands denies licenses to all fabs that produce advanced chips. Second, even if the Netherlands consistently denies licenses to these fabs, systems shipped to other Chinese fabs could later support AI chip production through diversion, cross-fab wafer processing, or unauthorized upgrades.

Public evidence suggests that at least some of China’s advanced fabs continue to obtain NXT:1980i systems. First, Anhui customs records and information from third-party contractors (Appendix E) suggest that CXMT, China’s flagship DRAM manufacturer and HBM producer, has continued to obtain NXT:1980i systems even after the Netherlands began requiring nationwide licenses in 2024. Second, Hua Hong is almost certainly preparing to launch a 7nm logic fab, consistent with public reporting (Appendix E) that it has previously obtained an NXT:2050i system (an investment that would make little sense absent plans for advanced-node production). Yet neither Hua Hong nor its subsidiary (Huali Microelectronics) have been added to the BIS Entity List, suggesting that US policymakers may have overlooked the company as an advanced-node producer. In April 2026, BIS reportedly issued “is-informed” letters directing US toolmakers to halt certain shipments to Hua Hong’s Fab 6 and the planned Fab 8a. It remains unclear whether the Netherlands matched that action through changes to its licensing policy, or whether Dutch authorities had previously granted Hua Hong licenses to import NXT:1980i. Even if Hua Hong is now effectively prohibited from obtaining NXT:1980i, it may have had over two years following China-wide Dutch controls to accumulate an NXT:1980i stockpile.

The same problem may recur over and over as China builds new fabs. China regularly establishes fabs through newly created corporate entities, creating a risk that a facility will obtain NXT:1980i before regulators recognize its plans for advanced-node production. US controls partially address this problem by requiring a license whenever the exporter knows that the covered equipment will be used for “advanced-node” production or if the end-use is unclear. It remains unclear whether the Netherlands applies an equivalent standard when reviewing licenses.

However, even under the most optimistic scenario—in which the Dutch government denies licenses for exports to fabs that support AI chipmaking, matching the scope of the US FN5 FDPR, and reliably identifies all such entities—China has at least four pathways to enlist NXT:1980i systems in support of AI chip production once they are in-country:

First, a fab could obtain NXT:1980i systems while producing legacy chips and subsequently upgrade the production line to an advanced node. Sometimes referred to as “diversion in place,” this practice violates export controls but is difficult to prevent. Chinese fabs have previously upgraded existing lines to new nodes, even at advanced nodes,^{Sidenote 63} making this scenario plausible.

Second, China could move NXT:1980i systems or their subsystems from an approved fab to a restricted one (“physical diversion”). China regularly diverts controlled technologies to restricted end users and facilities. The very continued existence of Huawei and its fab network (including its own fabs, SMIC, CXMT) involves a massive set of violations and diversion activities, illicit shipments, warehouse stockpiling, and wafer transfers between fabs. These violations have extended to advanced SME. For example, at the start of 2025, SMIC was reportedly able to divert controlled deposition, etch, and inspection/metrology equipment from non-advanced fabs owned by SiEn, Pensun, and Huawei’s Dongguan fab to its 7nm SN2 fab.

The risk of diversion is particularly high for NXT:1980i subsystems. Many key subsystems, including Cymer light sources, are smaller, less technically complex, and easier to transport and install than a complete DUVi system. For example, a legacy fab could import a replacement subsystem for an allegedly defective part in an installed NXT:1980i, then divert the replacement system to an advanced fab. The Dutch government may be able to mitigate this pathway by requiring end use verification as a condition of licenses for NXT:1980i subsystems, but enforcing such a condition across China’s fleet of approximately 270 NXT:1980i systems would require extensive on-site inspections or verification technology.

Third, China might route partially processed wafers between advanced and non-advanced fabs (“wafer diversion”), potentially dramatically expanding its advanced-node output. For example, an advanced fab at SMIC or CXMT might reserve a small number of more capable NXT:2050i or NXT:2100i systems for the most critical layers, while sending wafers to another fab’s NXT:1980i systems to pattern less demanding layers. Moving partially processed wafers between fabs is a recognized industry practice^{Sidenote 64} and Huawei has reportedly built infrastructure for transporting wafers between physically adjacent fabs. The principal technical challenge would be qualifying a single production process across multiple fabs. This challenge is substantial but likely surmountable, particularly when the participating fabs are nearby and controlled by a single entity or closely cooperating entities.

Finally, China could upgrade NXT:1980i systems after installation, exacerbating the impact of any of the preceding diversion pathways. ASML designed the NXT platform to allow machines to be upgraded after installation. Upgrades can improve several aspects of scanner performance, including overlay and alignment accuracy, imaging and focus control, and throughput. Dutch controls prevent ASML from improving the NXT:1980i’s throughput by more than 1 percent.^{Sidenote 65} Nevertheless, public reporting indicates that Chinese fabs have upgraded NXT:1980i systems, thereby improving 7nm production yields, by purchasing upgraded wafer stages, lenses, and alignment sensors through the secondary resale market and relying on Chinese vendors for installation and servicing.

China’s NXT:1980i stockpile could also accelerate its development of domestic lithography systems. A large installed fleet of NXT:1980i systems can supply grey-market components for domestic equipment;^{Sidenote 66} give Chinese engineers access to reference systems to study and reverse engineer; provide benchmarks for calibrating indigenous prototypes;^{Sidenote 67} and build tacit expertise among domestic engineers and maintenance technicians. However, a ban would provide a market opening for Chinese lithography makers; we do not assume either effect dominates.

In the near term, Chinese companies are unlikely to divert large numbers of NXT:1980i systems,^{Sidenote 68} though smaller-scale diversion remains plausible. Other SME bottlenecks—particularly limited access to advanced deposition and etch tools restricted by BIS between 2022 and 2025—independently constrain China’s advanced chipmaking capacity. These bottlenecks limit the additional production capacity unlocked by diverted NXT:1980i systems, reducing the immediate benefits of diversion.

China’s incentive to divert NXT:1980i systems will grow, however, as it develops domestic substitutes for an increasing share of the SME supply chain over time. As discussed in Section 3, lithography is likely to be the last major SME indigenized by China’s domestic industry. Once other bottlenecks in deposition, etch, metrology, and related process equipment are alleviated, the opportunity cost of keeping NXT:1980i systems on non-advanced lines will rise. If advanced lithography becomes the binding constraint on China’s AI chip production, China may become increasingly willing to accept the political risks associated with diversion.

7. A better alternative to exporting DUVi: dry DUV can support China’s legacy chips

Dry DUV systems—the generation of lithography tools that preceded DUVi—can support all of China’s legacy logic and memory nodes without enabling the nodes used to produce AI chips and HBM. By restricting DUVi exports while permitting dry DUV exports, the US and its allies can restrain China’s AI chip production without damaging its legacy chip production.

Dry DUV systems can support all of China’s legacy logic production. The majority of Chinese logic capacity is at 45nm or older nodes, which enable chips found in cars, household appliances, and industrial equipment. Advanced dry DUV systems are demonstrably sufficient for all of this production^{Sidenote 69} (Figure 13). A minority of its capacity extends to 28nm. At this node, China’s existing commercial processes incorporate DUVi systems (which were widely available by the time it was implemented), but experimental results and our own modeling find that dry systems can support this node as well. Our modeling estimates that ASML’s best dry DUV system (NXT:1470) can support 28nm with a modest yield penalty (Appendix C), using additional multipatterning. Industry history also supports the plausibility of extending dry DUV to the 28nm node. ASML marketed its XT:1450, an older dry DUV system, as supporting the development of 32nm node processes using double patterning. ASML’s NXT:1470 substantially improves on-product overlay compared to XT:1450 (from 7nm to 4.5nm), plausibly enabling it to extend into 20nm-class logic. Researchers have also experimentally demonstrated 45nm and even 32nm half-pitch patterns using dry DUV with double patterning, providing further evidence of its patterning capability.

For memory, the evidence is more limited but indicates that dry DUV systems are probably viable for DRAM nodes in the high-20nm range at least, including the 29nm node used for HBM1, with a modest yield penalty. The most relevant patterning evidence is Nanya’s sub-30nm DRAM study, which used a dry DUV tool to produce 30nm line/space patterns using self-aligned double patterning. Samsung’s study of 20nm honeycomb DRAM provides weaker, indirect corroboration by demonstrating that self-aligned patterning techniques can reduce a difficult capacitor-patterning sequence from three immersion exposures to one.

However, dry DUV is unlikely to enable the advanced nodes used for AI chips. For logic, we estimate (Appendix C) that NXT:1470 is very unlikely to achieve a viable yield for large 7nm dies. The first problem is alignment. NXT:1470’s published on-product overlay does not meet the effective 7nm overlay budget, increasing the risk of misalignment between layers and between multiple exposures within a single layer. Second, it is unclear whether NXT:1470 or any other dry system can implement a 7nm flow with sufficient control of individual features (e.g., cuts, contacts, and other critical features) due to critical-dimension nonuniformity, focus and dose variation, and pattern-dependent imaging errors. It is conceivable that a 7nm flow could be constructed using extremely restrictive design rules—e.g., highly regular, parallel lines with narrowly prescribed locations for cuts and contacts—but no such process has been demonstrated. Even if it proved technically feasible, these additional design restrictions would constrain circuit layout and routing, likely reducing chip density and performance and limiting the kinds of chips that could be produced.

For memory, NXT:1470 is highly unlikely to support 1x and effectively incapable of supporting 1y. At 1x, ASML’s illustrative flow specifies a 4nm on-product overlay budget, which is exceeded by NXT:1470’s 4.5nm on-product overlay specification, leaving no room for other edge placement errors (e.g., pitch walking). At 1y, both alignment and patterning constraints become tighter. Even with quadruple patterning, each individual exposure would approach NXT:1470’s 57nm resolution limit, leaving essentially no margin for error. Repeating these operations over many critical layers probably substantially reduces patterning yield.

8. The US government can control DUVi systems with executive branch authorities

China’s large and growing DUVi stockpile is the consequence of a policy choice to restrict only the most advanced lithography systems nationwide, while allowing earlier but still highly capable systems into the country and in some cases directly into advanced fabs.

To ensure that China cannot leverage foreign DUVi for AI chipmaking, the US must stop the flow of these systems into the country and develop enforcement mechanisms to prevent diversion of those systems that have already been stockpiled. The following actions would achieve these objectives.

First, the US government should ban new exports of any DUVi system nationwide to China, extending to ASML’s XT:1700i. The US government can implement this change by removing the dedicated chuck overlay (DCO) criterion in ECCN 3B001.f.1, with a policy of denial.^{Sidenote 70} After the change, China will be unable to import DUVi but still allowed to import dry DUV systems, which are unsuitable for AI chip production but sufficient for China’s legacy production.

To be effective, the US government will need to ensure that new controls apply to DUVi produced outside the United States by ASML and Nikon. There are four options for doing so:

• Option 1: The Dutch and Japanese governments apply equivalent controls alongside the US government, with a policy to deny all license applications. The Japanese and Dutch governments currently require a license for DUVi at or more advanced than NXT:1970i,^{Sidenote 71} but public evidence (Appendix E) shows that many licenses are granted. Additionally, as for US ECCN 3B001.f.1 and 3B993.f.1, the technical definitions used in Dutch and Japanese controls do not control earlier-generation ASML and Nikon DUVi systems that are nevertheless capable of producing advanced-node chips.^{Sidenote 72} Alignment with the US would require that the Dutch and Japanese governments remove the DCO parameter from their technical definitions and deny all licenses for DUVi systems covered by the license requirement. In advocating for this outcome, the United States can emphasize (see Section 9) that new controls are likely to shift semiconductor production outside of China, without affecting overall demand for DUVi.

If the Netherlands cannot be convinced to join in controls, the US government can pursue controls on foreign-produced DUVi in collaboration with Japan:

• Option 2A: The Japanese government restricts DUVi made in Japan and the US and Japanese governments control critical DUVi subsystems made in the US and Japan for Dutch DUVi systems otherwise destined to China. First, as in Option 1, the Japanese government can restrict all DUVi made in Japan. Second, all existing DUVi systems incorporate a light source—an irreplaceable technical subsystem used to generate deep ultraviolet light—from either a US company (Cymer) or a Japanese company (Gigaphoton). The US and Japan can jointly prevent DUVi exports to China, without the use of extraterritorial controls or needing cooperation from the Netherlands, by controlling their domestically produced light sources when the exporter has knowledge that the “end use” of that subsystem is incorporation into an ASML DUVi system destined to China.
• Option 2B: The Japanese government restricts DUVi systems made in Japan and the US government controls Dutch DUVi extraterritorially using the de minimis authority. First, as in Option 1, the Japanese government can restrict all DUVi made in Japan. Second, the de minimis authority allows the US government to control items produced abroad that incorporate more than a specified percentage of controlled US content. All existing ASML DUVi systems, including those without a US light source, incorporate some amount of US content, including wafer stages and US-origin integrated circuits. The US government can therefore control all ASML DUVi extraterritorially, without relying on cooperation from the Netherlands, by setting a 0% de minimis threshold for items meeting the revised thresholds in ECCN 3B001.f.1.^{Sidenote 73} It is possible that even Nikon DUVi systems made in Japan contain US-origin content that is difficult to remove, in which case Option 2B would not require Japanese collaboration. However, there is limited evidence as to whether this is the case, which is why Option 2B may require Japanese collaboration.

If neither Japan nor the Netherlands can be convinced to join in controls, the US government has the executive authorities required to unilaterally control all foreign-made DUVi systems to China:

• Option 3: The US government controls both Japanese and Dutch DUVi extraterritorially using the Foreign Direct Product Rule (FDPR). The SME FDPR allows the US government to control items produced abroad that are the direct product of US-origin software or technology. All existing DUVi systems meet this criterion because they incorporate integrated circuits that are presumed to be the product of US technology. At present, the US government carves out Japan and the Netherlands from the license requirement for items subject to the SME FDPR, including 3B001.f.1. The US government can enact extraterritorial controls by removing this carveout for 3B001.f.1 items. Ideally, Option 3 should be coupled with the US de minimis control in Option 2B to make it more technically and legally robust.

Second, the US government should restrict exports of DUVi subcomponents nationwide, including replacement parts for China’s existing DUVi systems. These replacement parts are at high risk of diversion from non-advanced to advanced fabs, as discussed above (see Section 6), making a nationwide license requirement essential.^{Sidenote 74} A key challenge is that China currently uses DUVi within many of its legacy fabs in addition to its advanced fabs; restrictions on replacement parts for those DUVi could therefore affect legacy production in addition to advanced production. To mitigate effects on legacy production, the US government could grant individual licenses for exports to legacy fabs while specifying end-use requirements (e.g., one-for-one replacement, regular inspections and reporting by ASML) that deter diversion.

Third, the US government should bar foreign nationals from servicing DUVi at China’s advanced fabs. The United States already prevents US toolmakers from performing any form of servicing at advanced fabs. However, Japan and the Netherlands restrict servicing only for specifically controlled tools, and prohibit a smaller set of activities, as discussed in Section 5. At legacy fabs, servicing should continue on condition that there is reporting and verification on the tool’s location and usage, one-for-one parts replacement, and periodic inspections.

• One way the US government can achieve this outcome is to convince the Netherlands and Japan to expand their controls to cover the full set of servicing activities and to apply those controls to DUVi systems.
• If either is unwilling, the US government has the authority to unilaterally ban servicing on DUVi located in an advanced fab using the EAR’s General Prohibition 10. This prohibition explicitly prohibits servicing of any item subject to the US jurisdiction when there is “knowledge” that an export control violation has or will occur “in connection with the item.” The US government has already declared that Chinese advanced-computing ICs are likely produced in violation of US export controls. After asserting jurisdiction over foreign-produced DUVi (see above), the US government can restrict servicing of DUVi at China’s advanced fabs by informing the public that there is a high likelihood that these DUVi are being used in connection with a violation of the US export controls, e.g. production of Huawei Ascend chips.

Fourth, the US government should work jointly with the Netherlands and ASML to detect and deter diversion of China’s existing DUVi stockpile. As discussed above (see Section 6), China has already imported a vast number of NXT:1980i DUVi systems to non-advanced fabs, which could massively accelerate AI chip production if diverted from non-advanced to advanced production. ASML probably has the capability to neutralize diversion using technical mechanisms.^{Sidenote 75} The US government should work with ASML and the Dutch government to obtain insight into this capability and ensure it is robust to countermeasures. Granting licenses for servicing at legacy fabs may also preserve ASML’s visibility into how those tools are used, reducing the risk of diversion.

Fifth, the US government should also work to restrict subcomponents, precursors, and knowledge transfers that enable China’s effort to indigenize advanced DUVi. Priorities include Zeiss projection optics, which are rumored to be entering China, together with the materials and equipment (e.g., fused silica) needed to make comparable lenses; high-power ArF excimer light sources and their subcomponents and consumables; and precision wafer and reticle stages and their motion sensors. See Appendix B for further discussion of DUVi subsystems. Although China will eventually indigenize commercially viable DUVi or more advanced lithography, delaying this point even by a few years could constrain its AI chip production even further, by postponing the subsequent ramp-up to reliable, high-volume manufacturing.

9. Banning DUVi exports would secure the US AI chipmaking advantage

Banning DUVi exports and servicing would reshape US-China competition in AI and semiconductors, with the following effects:

First, it would guarantee the United States and its allies a large AI chip production advantage over China through at least 2035. China’s current DUVi stockpile is physically incapable of matching the US-allied ecosystem’s AI chip production. Even if China overcomes every other SME bottleneck, diverts every NXT:1980i to AI chip production, and matches the throughput achieved in Western fabs, it would still produce far fewer AI chips than the US ecosystem (Figure 1, Appendix F). Continued DUVi exports would not automatically eliminate this advantage, assuming they are split between advanced and legacy fabs, but they would fundamentally alter the strategic situation. If China continues to import NXT:1980i systems at a similar volume as it did over 2024–2025 and were to mobilize this fleet for AI chip production (e.g., after indigenizing other SME bottlenecks), its annual output could reach hundreds of millions of NVIDIA H100-equivalents, enough to erase much of the US advantage and even surpass it under certain scenarios.

Second, China’s near-term AI production ramp would face additional barriers. First, China-wide DUVi controls would cut off the flow of new systems and subsystems that might otherwise benefit AI chip production, whether through licensed shipments or illicit diversion (Section 6). Second, enhanced restrictions on servicing of DUVi at SMIC, CXMT, and other fabs operating advanced production nodes would degrade the functionality of these tools, reducing overall yields and throughput, though there is some uncertainty as to the magnitude of this effect.

Third, new legacy fab construction in China would be unaffected. China’s legacy production nodes can be supported by dry DUV systems, as discussed above (see Section 7). These dry DUV systems would continue to enter China even after a ban on DUVi, enabling expansion of legacy capacity. Restrictions on replacement parts might degrade these DUV systems, but this impact can be mitigated by issuing individual licenses for verified legacy fabs.

Fourth, new advanced logic and memory production would shift away from China and towards the US and its allies. A nationwide ban on DUVi would make it far more difficult for China to expand capacity at advanced logic and memory nodes. With Chinese capacity expansions hobbled, demand for advanced chips would shift to fuel new fab expansions within the allied ecosystem. Recognizing this point, ASML’s previous CEO, Peter Wennink, stated in 2022 that even if China were “excluded from any growth,” new fabs would be built elsewhere and ASML’s 2030 outlook would not change much.

Fifth, US and allied memory foundries, logic foundries, and chip designers would benefit. For memory, US manufacturer Micron, Japanese manufacturer Kioxia, and Korean manufacturers Samsung and SK hynix face serious and potentially existential competitive threats from China’s leading fabs, YMTC and CXMT. China-wide DUVi restrictions would slow both firms’ near-term ramp at advanced memory nodes, particularly those needed to make HBM, and place a hard limit on their long-term capacity. Allied logic foundries like TSMC, Intel, and Samsung would similarly benefit from limitations on China’s leading logic fabs, particularly SMIC, ensuring US and allied leadership at the leading edge. Finally, US and allied chip designers also benefit relative to the status quo. Existing US rules likely already restrict these designers from manufacturing advanced chips at SMIC, while Huawei faces no such limitation.^{Sidenote 76} Further limitations on China’s advanced chip manufacturing will disadvantage Huawei in the global chip marketplace, bolstering allied designers.

Sixth, ASML would bear the primary costs among US and allied toolmakers, but these costs are modest and mostly recoverable.^{Sidenote 77} Assuming a complete restriction on DUVi sales and servicing to China, ASML could face revenue losses of ~$1–1.5 billion per year (3–4% of its annual revenue) but may be able to recover some of these losses. We break down ASML’s revenue losses and recuperation opportunities by tool and servicing revenue, as follows:

• Near-term tool revenue: ASML’s existing non-EUV backlog for other markets is large enough to cushion a cutoff for several months. At the end of 2025, ASML’s Chinese customers account for roughly €7.8 billion in backlog orders, while ASML’s overall non-EUV backlog is €13.6 billion, leaving €5.8 billion in non-China non-EUV orders.^{Sidenote 78} Even after a complete cutoff of Chinese DUVi sales, it would take months for ASML to run through this backlog.
• Longer-term tool revenue: Medium-term demand substitution would further cushion ASML’s equipment revenue. As fabs outside China expand to replace lost Chinese capacity, ASML would likely see increased orders from non-Chinese customers. ASML’s CEO Christophe Fouquet has indicated that ASML has mostly worked through its pandemic-era Chinese backlog and expects a rebalancing toward non-China demand. As mentioned above, ASML’s former CEO, Peter Wennink, stated that even if China were “excluded from any growth,” new fabs would be built elsewhere and ASML’s 2030 outlook would not change much.
• Near-term servicing revenue: ASML would lose up to roughly $1–1.5 billion per year from its Chinese servicing revenue (3–4% of ASML’s annual revenue), or less if servicing is restricted only at advanced fabs.^{Sidenote 79} Unlike equipment sales, which ASML can redirect to new fabs outside China, servicing revenue for installed-base tools in China would cease following a ban on servicing.^{Sidenote 80}
• Longer-term servicing revenue: ASML could fully recoup near-term servicing losses if servicing restrictions make China’s DUVi installed base non-functional or unusable. In this scenario, surging global chip demand would stimulate non-Chinese fab expansions and ASML would very likely sell equivalent or better DUVi to these new fabs, and then gain servicing revenue from those tools instead. On the other hand, ASML would not recoup near-term servicing revenue losses if China manages to keep DUVi systems online despite ASML withdrawing from servicing.

Even where ASML or other allied toolmakers suffer losses, the revenue at stake was in significant part enabled only by China’s subsidy program, which drives Chinese chipmakers to build more capacity than global market demand warrants. The part of the loss that would not shift to fabs elsewhere comes from the elimination of this subsidy-driven overcapacity as a revenue source.

Appendix A: AI chips made without DUVi are uncompetitive

We estimate the silicon area and power required to reproduce the aggregate peak compute throughput and memory bandwidth enabled by modern AI chips, using process nodes that can be implemented without DUVi. We use NVIDIA’s announced B100 configuration as a reference, which is manufactured using TSMC’s 4NP logic process (a variant of 5nm) and SK hynix’s HBM3e, based on the 1β DRAM node. We compare the B100 with hypothetical chips built using 28nm logic and 29nm DRAM, which we separately estimate (Appendix C) to be the most advanced nodes achievable using dry DUV lithography.

Logic scaling

Advanced nodes enable logic processors with higher transistor density and improved performance per watt. Transistor density varies between different silicon structures (e.g., high-performance standard cells, SRAM, analog circuitry, and I/O), so the density of a given product depends on its internal composition. We estimate density scaling using two methods:

• Method 1 uses density proxies for high-performance (HP) cell libraries. AI chips devote a large fraction of their area to performance-critical logic implemented with high-drive standard cells. Applying these densities to whole chips is an approximation, because SRAM, analog circuitry, and I/O scale differently from HP logic.
• Method 2 compares densities of NVIDIA GPUs at each node, obtained by dividing published transistor counts by total die areas. This method captures a realistic mixture of logic, SRAM, and I/O, but is potentially confounded by architectural differences between chips.

In addition to transistor density, clock frequency also affects compute throughput per area. Clock frequency depends on a variety of factors, including pipeline design and voltage characteristics, as well as the process node. We assume that a design adapted for 28nm can match the B100’s compute clock, which is supported by high-frequency 28nm arithmetic results. However, this has not been verified and remains a source of uncertainty.

We estimate power scaling using three methods:

• Method 1 backchains TSMC’s claimed reductions in iso-performance power efficiency across nodes. This method is internally consistent but reflects scaling for test designs operating at favorable voltages. It also does not fully capture the weaker scaling for SRAM, analog circuitry, and I/O, and assumes that designers use each node to minimize power rather than increase frequency.
• Method 2 estimates the gains realized in product-like implementations. We use data from shipped GPUs and normalize to account for changes in architecture, numerical precision, and voltage/frequency operating point.
• Method 3 compares ports of the same or similar register-transfer level (RTL) across different nodes.

For the chip comparison below, power Methods 2 and 3 provide the more appropriate estimate.

DRAM scaling

Advanced DRAM nodes enable HBM with improved capacity, bandwidth, and power efficiency. Higher bit density increases capacity per unit silicon area, which particularly benefits HBM by offsetting the area occupied by TSVs and peripheral circuitry.^{Sidenote 87} Lower energy per bit reduces the stack’s power consumption and overall thermal load,^{Sidenote 88} enabling higher stack heights, increased capacity, and higher sustained bandwidth before the stack reaches thermal limits. Finally, faster transistor switching speeds enable higher per-pin signaling rates and therefore higher bandwidth.

Matching B100 FLOPS and Bandwidth using 28nm logic and HBM1

We estimate the logic die area, memory die area, and power consumption required to match the B100’s peak processing performance (3,500 TFLOPS at dense FP8) and memory bandwidth (8 TB/s).

• Logic die area: We estimate a 9.6× density penalty, averaging the 4NP-28nm ratios implied by density Methods 1 and 2. Assuming a similar compute architecture, area composition, and clock speed, matching the B100’s 3,500 TFLOPS of dense FP8 compute (~2.2 TFLOPS/mm² across an estimated ~1,600 mm²) therefore requires 15,400 mm² of logic silicon, distributed across 20 dies of up to 800 mm² each.
• Memory die area: Matching the B100’s 8 TB/s bandwidth requires 62.5 HBM1 stack-equivalents at 128 GB/s per stack. The per-stack bandwidth already incorporates interface signaling speed, so no additional memory-clock multiplier is applied. We model HBM1 at 4 GB/stack, which is supported by the HBM1 specification, rather than the initial 1 GB/stack configuration.^{Sidenote 90} At an assumed effective HBM1 density of ~0.057 Gb/mm²,^{Sidenote 91} the resulting 250 GB of memory requires ~35,000 mm² of DRAM die area. This notably corresponds to ~250GB of capacity, 1.3× more than the B100.
• Power consumption: We assume a compute-bound workload and decompose the B100’s 700 W TDP using measurements from the H200, whose six HBM3e stacks consume ~150 W under a 700 W compute-bound workload. Scaling to the B100’s 8 HBM3e stacks implies ~200 W of HBM power and ~500 W for the logic dies. We scale logic power consumption by 5.44×, the midpoint of the power penalties implied by Methods 2 and 3 above, giving 2,720 W. For memory, we assume a 1.73× compute-bound power penalty, using 7 pJ/bit for HBM1 and 4.05 pJ/bit for HBM3e as a proxy. Scaling the same 200 W baseline gives ~346 W of memory power and ~3,066 W in total, rounded to ~3,100 W, or 4.4× the B100’s TDP.

Caveats

1. This comparison calculates the number of legacy AI chips needed to achieve the B100’s FLOPS and memory bandwidth, but aggregating legacy chips may not necessarily translate to equivalent system-level performance. This is because a network of less powerful legacy chips would require substantially more networking complexity than a B100, introducing power, latency, packaging, and system availability challenges.
2. Logic die area is scaled based on transistor density while assuming a similar clock speed. There is some evidence that 28nm chips could be clocked to match B100, but this is not well established. If clock speed is reduced, it will increase the required die area proportionally. Conversely, Section 7 notes that NXT:1470 could plausibly reach 20nm-class logic. TSMC’s stated 1.9× density gain from 28nm to 20nm (footnote 81) would cut the logic-area penalty to roughly 5×.
3. We assume 29nm DRAM enables HBM1 because HBM1 was historically demonstrated at this DRAM node. But the DRAM node does not uniquely limit HBM bandwidth. Advanced signaling, peripheral circuitry, or packaging could enable 29nm DRAM to achieve greater bandwidth per stack than historical HBM1.

Appendix B: Technical challenges of developing advanced lithography

The challenge of developing an advanced lithography system is threefold. First, a large number of specialized subsystems must be developed to an extremely high standard of performance. A few of the most challenging subsystems^{Sidenote 92} are as follows and shown in Figure 17:

• The light source generates the 193nm DUV light used to print patterns on the wafer and must fire high-power pulses thousands of times per second while keeping wavelength, bandwidth, and delivered dose extremely stable over billions of pulses.^{Sidenote 93}
• The illumination optics subsystem shapes and homogenizes the DUV light before it reaches the mask in order to achieve the desired balance between resolution, depth of focus, and process window.^{Sidenote 94}
• The projection optics subsystem projects the patterned light from the mask onto the wafer and must maintain extremely low optical distortion and aberration.^{Sidenote 95}
• Reticle and wafer stages move the mask and wafer in precise synchronization during each exposure and must achieve sub-nanometer positioning accuracy while accelerating rapidly enough to enable high throughput.^{Sidenote 96}
• Alignment sensors ensure that each layer is correctly registered to the layer beneath it, requiring them to correctly measure and correct for tiny positional errors on the wafer in real time.^{Sidenote 97}
• Leveling and focus sensors ensure the projected image stays in focus by measuring wafer height, topography, and deformation in real time.^{Sidenote 98}
• The immersion hood maintains the ultra-pure water layer between the final lens and the wafer and must eliminate bubbles, escaped droplets, contamination, thermal non-uniformity, and wafer-edge defects, without sacrificing throughput.^{Sidenote 99}

Second, these subsystems must be made to work together as a single machine. ASML does not publicly disclose a parts count for DUVi systems, but its EUV machines, which are built on the same TWINSCAN platform, contain about 100,000 individual parts. Coordinating a machine of this complexity requires an elaborate control system, including dozens of networked microprocessors, hundreds of actuators, hundreds of thousands of sensors, and millions of lines of code—a codebase ASML says has been under continuous development for 30 years. Complexity of integration scales with the number of components, as changes to one subsystem affect the performance of others. For example, in a DUVi system, the water touches both the lens and the photoresist coating on the wafer, so chemicals from the resist can leach into the water and contaminate the lens. Solving this problem required coordinated industry co-development of the projection optics, immersion hood, water-purification system, and new low-leaching resists and protective coatings.

Third, the integrator must coordinate the enormous network of research, engineering, manufacturing, and transportation required to build machines at production scale. ASML says that roughly 85% of the components in its machines are manufactured by its network of over 5,000 suppliers. At least 700 of these contribute to advanced lithography and 200 contribute components that ASML considers critical and single-source. Some of these partners are effectively irreplaceable. Most notably, Carl Zeiss SMT has been ASML’s sole supplier of lenses, mirrors, illuminators, collectors, and other critical optics. US company Cymer^{Sidenote 100} and Japanese company Gigaphoton are the dominant suppliers of DUV light sources. Other specialized subcomponents are drawn from specialists scattered across the Netherlands, Germany, the US, the U.K., Switzerland, and Japan. ASML serves as the master integrator. It aligns suppliers’ technical roadmaps and production capacity, manages the logistics around component shipments, and coordinates the technical integration itself. ASML treats management of its supplier network as a core capability. Former Chief Strategy Officer Frits van Hout described the company as engineering its supplier relationships “like a machine,” and ASML has gone as far as providing capital injections or acquiring suppliers outright^{Sidenote 101} when necessary to preserve critical supply capability and production capacity. A non-exhaustive list of key supplier relationships is provided in Table 8:

Appendix C: DUV frontend logic yields

We estimate perfect die yields, not accounting for salvaged dies, achievable using a range of DUV systems at various logic and memory nodes, assuming a mid-sized (500 mm²) logic die and a mature production process at an industry-leading fab (e.g., TSMC for logic, SK hynix for DRAM) with state-of-the-art SME (etch, deposition, etc.) outside of lithography. The reported ranges are for the P10, P50, and P90 of the distributions produced by running Monte Carlo simulations sampled from various input distributions, described below. See Figure 10.

Caveats

Die yield is among the most closely guarded figures in semiconductor manufacturing and depends vitally on proprietary, undisclosed process knowledge. Published figures are scarce and rarely provide context that supports interpretation. Reconstructing yield for a particular node and tool therefore requires assembling evidence from a variety of disparate sources, none of which was intended to enable analysis. The method presented here draws what conclusions the limited public record will support.

We have quantified some uncertainty using Monte Carlo techniques. However, this does not capture uncertainty in the structure of the model itself or in the applicability of the anchoring sources to the processes modelled.

Overall, this analysis should be read as providing limited direct evidence for three claims, supplementing indirect evidence that can be inferred from the industry’s historical record:

1. NXT:2100i, NXT:1980i, and NXT:1470 are all viable at 28nm.
2. NXT:2100i and NXT:1980i are viable through at least 7nm.
3. NXT:1470 is almost certainly not viable at 7nm and of limited viability at 16/14nm.

The exact numerical differences between individual cells warrant less weight than these high-level conclusions.

Methodology

We model frontend yield using a Monte Carlo simulation with 100,000 draws. Inputs with uncertainty are specified using quantiles (P10, P50, P90) and fitted using a log-normal distribution for positive quantities and on the logit scale for decimal quantities. Each draw samples every input once and applies the same shared draw across all node and tool combinations.

We model yield as the product of wafer-level line yield and three die-yield factors. Y_line and Y_{nonpatterning, residual} are not affected by lithography tool quality, while Y_random and Y_patterning vary with tool quality.

Modeling Y_line

Y_line, line yield, is the fraction of wafers that complete wafer fabrication and can be available for die sort. Line-yield losses include broken or scratched wafers, unrecoverable equipment failures, or gross misprocessing. The general relationship is:

We approximate line yield using node-specific constants:

A 2002 survey of 10 high-performing fabs (CSM-52, Figure 3-1) reported roughly 98% line yield per 20 mask layers; a 2010 NAND study independently estimated 98% (though this finding is given slightly less weight as the study was for NAND memory). We estimate modestly lower yields because advanced-node processes have many more layers (e.g., up to 80 for 7nm with immersion), creating more opportunity for losses. On the other hand, improvements since 2023 in automation, reliability, process control, and excursion containment likely counteract this effect. Balancing both considerations and factoring an estimate from a semiconductor industry expert, we use [95, 98, 99] at 28nm and [93, 97, 99] at the more advanced nodes. Because we do not mechanically scale line yield with every mask equivalent, this approach may slightly overestimate yield for long processes, particularly implementations of advanced nodes using dry DUV tools.

Modeling Y_{nonpatterning, residual}

Y_{nonpatterning, residual}, residual non-patterning yield, accounts for systematic and parametric die loss caused by non-patterning process variation or design-process interactions not already counted in random, patterning, or line yield. Examples include transistor-parameter variation, implant and doping variation, and wafer-edge integration losses not attributable to pattern placement. A mature fab can eliminate most of these failures, but others are unfixable. The general relationship is:

We approximate this as a constant with quantiles:

Across the 11 devices in Table 3 of the SEMATECH-sponsored survey, systematic-limited yields are approximately [70, 87, 96]%. These include lithography losses modeled separately here. An industry expert familiar with the program reported that its population also included DRAM, whose more regular, redundant structure may yield better than a large logic die. After separating patterning losses, allowing for improved process control, and biasing moderately upward to reflect the assumption of a world-leading fab, we use [88, 94, 99]%.

Modeling Y_random

Y_random, random defect-limited yield, accounts for die loss due to random, non-systematic killer defects, such as particles, residues, voids, and localized opens or shorts, whose incidence increases roughly in proportion to the length of the manufacturing process. We model Y_random using a negative binomial, reflecting standard modeling approaches from the literature:

We estimate A as [400, 450, 475] mm², less than the physical 500mm² because some area is allocated to repairable SRAM,^{Sidenote 103} which we estimate occupies 5–20% of the overall die.

We model PL_node,litho as:

We assume NXT:2100i and NXT:1980i have the same process length because both have the same 38nm resolution. NXT:1470 has a looser resolution (57nm) and thus requires additional multi-patterning steps above and beyond NXT:2100i/1980i, increasing process length. These additional steps include (i) pitches between 76–114nm, which can be single-patterned with DUVi but require SADP using the NXT:1470, and (ii) pitches between 38-57nm, which can be patterned with SADP using DUVi but which require another pitch multiplication using NXT:1470.

We anchor estimates of D_0,random on 7nm with immersion, for which we estimate D₀ ≈ [0.05, 0.06, 0.09]. P90 reflects public reporting that TSMC’s N7 process launched in 2018 using NXT:1980i and ramped to D₀ ≈ 0.09 defects/cm² within three quarters. P50 reflects benchmarking at older nodes, which found the best fabs achieved a D₀ at 0.06, and the likelihood that TSMC’s D₀ continued to decline. P10 reflects the lower bound of recent analyst estimates claiming D₀ ≈ 0.05–0.15 for a mature node.

We linearly scale D₀ to other nodes and to processes using NXT:1470, deriving the following yields:

Modeling Y_patterning

Y_patterning, patterning limited yield, accounts for die loss caused by failure to form patterned features within their allowed geometric tolerances. It includes overlay errors between layers and between multiple exposures within a layer, as well as residual non-overlay errors arising from critical-dimension variation, focus and dose variation, and pattern-specific imaging limitations, among others. We model Y_patterning as:

Y_overlay is modeled as the magnitude of two independent Gaussian-distributed registration errors, reflected by a Rayleigh distribution:

The model assumes that overlay errors scale linearly with the number of critical exposures and with die length, rather than die area, reflecting the fact that overlay errors are typically moderately spatially correlated. Notably, industry experts indicate that actual overlay loss is often dominated by one or two product- and process-specific layers, while other layers with similarly tight specifications contribute little measurable loss. Public information is not sufficient to identify or analyze the key layers in relevant products, so we retain the transparent count-based approach.

We fit the model using published data from ASML at the 20nm node. ASML’s 2014 investor-day presentation estimated less than 1% overlay yield loss for a 100mm² 20nm logic die when the 5nm on-product overlay specification was met, versus ~4% loss when it was exceeded by 20% (6nm on-product overlay, or OPO), assuming 14 immersion passes. Fitting these observations with A₀ = 100 mm² and L₀ = 14 yields κ = 4.6.^{Sidenote 110}

We apply this model for each combination of NXT tool and node. We assume OPO of [1.5, 1.75, 2.0]nm for NXT:2100i,^{Sidenote 111} [3.0, 3.25, 3.5]nm for NXT:1980i, and [4.25, 4.5, 4.75]nm for NXT:1470. We assume node OPO specs of [5.75, 6.0, 6.25]nm at 28nm, [3.75, 4, 4.25]nm at 16/14nm,^{Sidenote 112} and [2.75, 3.0, 3.25]nm at 7nm.^{Sidenote 113} We estimate overlay-critical exposure counts by anchoring to ASML’s disclosed 14 overlay-critical immersion passes at 20nm and scaling across nodes with two triangulating methods: (i) ASML’s published lithography-step counts for a fixed critical-layer stack (6/8/23/34 steps at 28/20/10/7nm) and (ii) a bottom-up decomposition of each node’s known patterning schemes, counting every split, mandrel, block, and cut exposure at layers whose overlay budget is within ~1.5× of the node’s tightest spec. Counts are identical for all immersion tools. For the NXT:1470, we estimate extra exposures required for layers that newly require advanced patterning.

Under these assumptions, we find the following yields:

Y_{residual, non-overlay} captures patterning failures within a single exposure, particularly critical-dimension (CD) variation, focus/dose variation, line-edge roughness, and optical proximity correction (OPC) errors. This factor is probably small when the lithography system can support the node within its process window but expands dramatically when the process window is exceeded.

We estimate [0.97, 0.98, 0.99] for NXT:2100i and NXT:1980i at all three nodes, and for NXT:1470 at 28nm. The UC Berkeley study of mature fab yields, co-sponsored by SEMATECH, found that the best processes achieved 96–98% total systematic yield, with losses split between lithography and other process steps. ASML/Brion’s 2019 voltage-contrast study provides complementary evidence that even with overlay minimized, local edge placement error generates a small, residual loss.

• For NXT:2100i and NXT:1980i, there is strong evidence that residual loss is minimized. NXT:2100i was used for the most critical layers at 7nm and for critical immersion layers at 3nm and below. ASML explicitly characterized NXT:1980i as an immersion scanner for 7nm and 5nm production nodes, and NXT:1980i provides the same 1.35 NA and 38nm resolution as NXT:2100i;^{Sidenote 114} NXT:2100i’s capability is thus partial evidence that basic optical resolution is not a limiting problem for NXT:1980i.
• For NXT:1470 at 28nm, evidence also suggests minimal residual yield loss. First, ASML claims that XT:1450, an older dry ArF system with worse process control, is sufficient for high volume manufacturing at the 32nm node. Second, the even older XT:1400E was experimentally found to support extending capability beyond 32nm, “towards the 22nm node,” and to enable printing 40nm contact holes with an 80nm pitch (tighter than the 28nm node’s ~113nm contact pitch requirement). Third, ASML found that dry ArF systems can achieve 40nm half pitch, tighter than the 45nm half pitch required for 28nm’s tightest metal layer (M1).

For NXT:1470 at 16/14nm and 7nm, we estimate [0, 0.5, 0.98], reflecting wide uncertainty as to whether these nodes can be implemented. The P10 reflects a judgment that outright infeasibility cannot be ruled out, particularly at 7nm. On the other hand, it is possible that a workable process can be obtained, particularly for products with highly restrictive design rules, that could minimize this yield factor. This factor is the dominant source of uncertainty for the two affected cells, and the resulting yield ranges should be read as incorporating fundamental uncertainty about the feasibility of implementing these nodes using NXT:1470.

Appendix D: DUVi throughputs for Huawei AI chip production

We estimate the throughputs of the advanced DUVi systems within China’s installed base for producing Huawei’s Ascend 910C chips, in two scenarios: (1) usage within mature advanced fabs (e.g., TSMC, SK hynix) achieving industry-leading die, stacking, and packaging yields, and (2) usage within China’s fabs (e.g., SMIC, CXMT), providing substantially lower yield. The reported ranges are for the P10, P50, and P90 of the distributions produced by running Monte Carlo simulations sampled from various input distributions, as described below. See Figure 11.

The estimates represent the number of finished Ascend 910C-equivalent packages that could be supported by the wafers patterned by one scanner in a single month, conditional on sufficient complementary equipment and packaging capacity.

Methodology

We estimate throughputs for each DUVi system when producing the two silicon inputs to the Ascend 910C: 7nm logic dies, and HBM2e stacks using 1y DRAM dies. For each input, we estimate output per scanner as a function of (i) the scanner’s wafer-pass throughput, (ii) the number of DUVi wafer passes required per wafer, (iii) the number of dies obtainable per wafer, (iv) die yield, and (v) for HBM2e, backend stacking yield. Dies are converted to Ascend 910C-equivalents assuming two 7nm logic dies and 64 DRAM dies (eight 8-Hi stacks of HBM2e) per chip. This produces an estimate of the number of chips that the scanner could support if solely dedicated to logic or to memory. Last, we estimate an optimal allocation of the tool fleet between logic and memory and apply a CoWoS packaging yield factor, producing the final estimates.

We model production occurring in two scenarios: (1) a mature advanced fab (e.g., TSMC for logic, SK hynix for HBM), with industry-leading die, stacking, and packaging yields, which bounds output from above, and (2) China’s advanced fabs (e.g., SMIC for logic, CXMT^{Sidenote 116} for HBM), with substantially lower yields. The second scenario is useful for estimating DUVi production in China under current conditions, though only under the critical assumption that sufficient complementary SME exists to reach DUVi throughput limits.

We model input uncertainty by specifying three quantiles (P10/P50/P90). Inputs representing positive quantities are fitted in log space; inputs representing yields are fitted in logit space. We run 100,000 Monte Carlo simulation draws, each of which samples one internally consistent set of parameter values and evaluates the full model, including the tool allocation step.

Caveats

Beyond explicitly modeled uncertainties, this overall analysis has four notable conceptual limitations:

1. We assume DUVi is the sole constraint on Ascend 910C throughput—i.e., that there is a limitless supply of other (non-litho) frontend tools and advanced packaging capacity. In reality, both the US-allied and Chinese semiconductor ecosystems face additional constraints on throughput. In particular, China’s advanced node production is constrained by limited availability of etch and deposition tools. Until this bottleneck is overcome, China’s production throughput would be unchanged even if many more DUVi systems were diverted to 910C production. These estimates should therefore be understood as assessing the throughput of DUVi in the absence of these other constraints.
2. We assume that logic and HBM are independent bottlenecks to production, in which case throughput is maximized by allocating DUVi between logic and HBM in proportion to their contribution to the Ascend 910C. In reality, production is likely to be bottlenecked on either logic or HBM, but not both—e.g., as of spring 2026, HBM, not advanced logic, bottlenecks both the Chinese and the US ecosystem. Each additional DUVi provides a much greater boost to throughput in this scenario, because the fab can allocate its productive capacity towards alleviating one bottleneck rather than splitting it between two.
3. Estimates depend on the Ascend 910C’s specific technical architecture, including the specific choice of nodes (7nm logic, 1y DRAM, HBM2e) and the ratios of silicon usage. They would differ for chips using alternate nodes, technologies (e.g., GDDR), and proportions.
4. Each HBM stack also contains a logic base die, which might also require immersion passes if fabricated using advanced nodes. We exclude base dies for simplicity and because public information does not establish that base dies would require advanced immersion. However, this remains a major source of uncertainty.

Wafer-pass throughput

ASML rates the NXT:1980Di at 275 wafers per hour, and the NXT:2050i and NXT:2100i at 295 wafers per hour. These imply theoretical maxima of approximately 198,000 (NXT:1980Di) and 212,000 (NXT:2050i/2100i) wafer passes per month at continuous operation.^{Sidenote 117} In practice, throughput is a fraction of the rated maximum, since ratings assume benchmark exposure conditions and continuous availability.

Later NXT:1980i variants have higher rated throughputs (295 wafers/hour for NXT:1980Ei and 330 for NXT:1980Fi). To model a blended mix of NXT:1980i scanners, we apply a flat 5% increase on top of the realized estimated NXT:1980Di throughput.

Logic

The Ascend 910C co-packages two 7nm logic dies, with a combined area of 1,300 mm², or roughly 650 mm² per die. Throughput for manufacturing these dies depends on (i) wafer-pass throughput (see above), (ii) the number of DUVi wafer passes required per 7nm wafer, (iii) the number of dies produced per wafer, and (iv) the fraction of dies produced that are sellable.

These factors combine as follows:

HBM

The Ascend 910C includes 8 stacks of 8-Hi HBM2e, incorporating a total of 64 1y DRAM dies. Throughput for producing HBM depends on the four factors above—dies per wafer, exposures per wafer, exposures per month, die yield—and an additional multiplicative yield factor capturing loss from stacking DRAM dies into HBM. We estimate these as follows:

Combining factors as above, we have:

Ascend 910C

We convert the above throughputs to Ascend 910C-eq, assuming two logic dies and 8 HBM2e stacks per chip:

Assuming no independent constraints on either HBM or logic production, overall Ascend 910C throughput is balanced by allocating tools in inverse proportion to their Ascend 910C logic and memory throughputs. This allocation is computed separately for each draw, so the ratio varies. For example, at the median of the SMIC/CXMT scenario, approximately 2.4 NXT:1980i systems are allocated to CXMT’s HBM production for every tool allocated to SMIC’s logic production. With the tool fleet split in these ratios, the blended throughput of 910C-equivalent silicon (T_blended) is the harmonic combination:

Finally, we multiply by an advanced packaging (CoWoS or other) yield factor, accounting for loss during advanced packaging, estimated at [97, 98, 99]^{Sidenote 135} for a mature fab and [65, 75, 85]^{Sidenote 136} for SMIC/CXMT to get our final estimates for finished 910C chips per DUVi system.

Appendix E: Assessing China’s DUVi installed base

We estimate that China imported 396 DUVi systems between 2012 and 2026Q1 (with a central 80% model range of 361 to 444). Subtracting an estimated 42 / 52 / 67 imports at four multinational fabs yields an estimated 312 / 343 / 383 systems imported for Chinese-owned fabs. Within the Chinese-owned subtotal, we estimate 29 / 45 / 69 NXT:1970i and less advanced systems, 249 / 270 / 294 NXT:1980i systems, 22 NXT:2050i systems, and six NXT:2100i systems. These figures represent cumulative imports rather than operational scanners; retirements and re-exports are not modeled, and imports before 2012 are excluded. We limit our focus to ASML’s systems, rather than Nikon, which has minimal market share for advanced systems.^{Sidenote 137}

Alongside this aggregate estimate, we estimate installations at (i) SMIC’s Beijing and Shanghai fabs, including the Shanghai campus used for 7nm logic, (ii) CXMT’s Hefei and Beijing fabs, (iii) fabs owned by non-Chinese multinationals, (iv) all advanced logic and DRAM fabs owned by Chinese companies, (v) YMTC, China’s leading NAND producer, and (vi) select other publicly documented fabs. These estimates have varying evidentiary status. The SMIC and CXMT figures are fab-specific estimates; advanced-logic and advanced DRAM totals are broad allocation estimates; “other known installations” are partial observations; and the multinational estimate is an undifferentiated ownership allocation. Public data do not enable a comprehensive fab-by-fab accounting: the entity-level figures below include only systems we can estimate or document, while “unknown” captures the remainder.

Unless otherwise stated, ranges report P10 / P50 / P90. Quantiles are calculated after aggregation and subtraction within each Monte Carlo draw, so they need not add or subtract exactly.

China has probably imported DUVi systems since at least SMIC’s first introduction of the 45nm logic node in the late 2000s. From 2012 onward, China imported modest but growing numbers of earlier-generation systems; after NXT:1980i became available in the late 2010s, it began importing those systems as well, reportedly accumulating up to 80 by fall 2023. Imports accelerated sharply in 2023, after the United States and the Netherlands announced tighter controls. During 2023, Chinese fabs imported six NXT:2100i systems, 16 NXT:2050i systems, and 35 NXT:1980i systems. From 2024 to 2026Q1, China more than tripled its stockpile of NXT:1980i systems.

China’s aggregate installed base

We estimate cumulative DUVi imports attributable to Chinese-owned fabs over 2012–2026Q1, in two stages. First, we reconstruct gross annual imports into China, using ASML’s public financial disclosures, China’s customs statistics, shipment figures published by the Select Committee on the CCP, and public estimates of China’s installed base as of 2023. Second, we estimate imports to four multinational fabs (Intel Dalian in Liaoning, Samsung Xi’an in Shaanxi, and SK hynix Wuxi and TSMC Nanjing in Jiangsu) and subtract these imports from the gross estimate.

We report ranges for the P10, P50, and P90 of distributions produced by running 100,000 Monte Carlo simulations sampled from uncertain input distributions specified by P10, P50, and P90 quantiles. Positive-valued inputs are sampled from two-piece lognormal distributions fitted separately to their upper and lower quantiles. Pricing and ASML-finance assumptions are drawn once per simulation and applied across years, because errors in these assumptions affect all such years. By contrast, assumptions about customs data are drawn separately for each province-year observation, reflecting observation-level uncertainty in customs classification, coverage, and valuation.

Estimate from ASML’s financial data

ASML’s financial disclosures report its ArFi revenue share, worldwide ArFi shipments, EUV revenue share, and share of revenue attributable to customers in China. All revenues use net system sales, excluding servicing and field options. We estimate ASML’s China ArFi revenue as:^{Sidenote 138}

This method has two important limitations.

• First, it assumes that the composition of ASML’s China system revenue resembles the composition of ASML’s non-EUV system revenue outside of China. The direction of the resulting bias is unclear. On the one hand, non-Chinese customers plausibly spend less on dry DUV because they typically invest less in legacy nodes. On the other hand, access to EUV may reduce their spend on DUVi as well. We account for this uncertainty using a multiplier on ASML’s China ArFi revenue, with quantiles [0.8, 1, 1.2].
• Second, it assumes that Chinese customers purchase the same mix of DUVi models as customers outside of China. This assumption is almost certainly incorrect, because controls from 2023 onwards restrict NXT:2000i and more advanced systems, concentrating later purchases in the less expensive NXT:1980i. Comparing ASML’s worldwide blended DUVi revenue to China’s DUVi revenue may understate the number of systems China purchased. We account for this uncertainty using a multiplier on China’s ArFi price, with quantiles [0.8, 1, 1.1].

Estimate from China’s customs data

China’s public customs statistics portal reports the quantity and declared import value of lithography equipment under HS codes 84862031 (“Step and repeat aligners (steppers) for manufacturing semiconductor devices or integrated circuits”) and 84862039 (“Other lithography equipment”), for each Chinese province. The limitation of this dataset is that it does not identify scanner models. NXT:1980i systems are aggregated with earlier DUVi, dry DUV, and i-line, and potentially other equipment classified under the same codes.

For each province and year, we treat the reported quantity and value as deriving from a three-part mixture of:

• NXT:2050i and NXT:2100i systems, for which shipments are independently known;
• residual immersion-priced systems, labeled “DUVi-priced units” in 2015–2020 and used as an NXT:1980i proxy from 2021 onward; and
• dry DUV and less advanced (e.g., i-line) systems.

where:

• ASP_dry is estimated at $[9, 12.5, 15] million, calibrated based on (i) ASML financial data (Table 35) and (ii) customs import values and quantities over 2021–2024, in which the Select Committee data confirms import quantities for NXT:1980i, 2050i, and 2100i. The customs method estimates ASP of $12.6 million, while the ASML method estimates $12.5 million.
• Shipments_≥2050i are estimated in Table 27:

• ASP_≥2050i is estimated at $90M (Table 35) with multiplier [0.8, 1, 1.2]
• ASP_immersion is estimated for 2015–2020 using ASML’s worldwide blended ArFi ASP: worldwide ArFi net system sales divided by worldwide ArFi units. From 2021 onward, price residual immersion units as NXT:1980i, supported by data from the Select Committee on China, and modeled as a linear interpolation between $63M in 2018 (Table 35) and $76M in 2024 (estimated using ASML financial disclosures and Select Committee shipment numbers as $6,853M / 90 = $76M). For 2025–2026Q1, it is scaled in proportion to the blended DUVi ASPs (Table 35). We apply a [0.8, 1, 1.2] price multiplier.

We can now generate the following estimates for residual immersion-priced units.

The customs method has several limitations. First, the HS codes might include a variety of equipment beyond new ASML scanners, including non-ASML equipment, used equipment, or ancillary items classified as lithography machinery. Second, declared value may also differ from ASML pricing because of freight, insurance, configuration, transfer pricing, or the treatment of system modules. Third, the reported province is normally the registration location of the importer or consignee, which may differ from the system’s ultimate installation location. Finally, known shipments cover only 19 of 22 reported NXT:2050i systems shipped to Chinese fabs, leaving three unassigned. Those systems may remain embedded in the residual estimates above.

We account for uncertainties in customs accounting using multipliers with quantiles [0.9, 1.0, 1.05] but do not attempt to account for incomplete identification of advanced systems or errors in reported provinces.

Consolidated estimate

The consolidated model selects the strongest available source for each period and triangulates between sources when no direct shipment is available. For 2012–2014, before customs data is available, we use the ASML financial estimate alone. For 2021–2024, we use the Select Committee’s shipment numbers (Table 38). These are the most direct public estimates available and distinguish NXT:1980i, NXT:2050i, and NXT:2100i, and are not modeled with uncertainty. For 2015–2020 and 2025–2026Q1, we combine the ASML financial estimate and the customs estimate. Over their common 2015–2026Q1 span, the ASML and customs methods broadly align, at 294 / 379 / 494 and 317 / 389 / 501, respectively. We combine them as follows:

We use a public estimate from November 2023, which claims that China had no more than 80 NXT:1980i systems at that time, to estimate installations prior to 2021 (the first year for which we have data from the Select Committee), with modeled uncertainty [0.25, 0.5, 0.75] as to the fraction of known 2023 shipments incorporated into the estimate. All remaining pre-2021 systems are classified as NXT:1970i and older.

For 2021–2024, the Select Committee estimates represent Chinese-owned fabs. For other years, we subtract estimated imports to multinational fabs (described below) from the gross estimate, year by year within each Monte Carlo draw. For 2012–2017, we deduct multinational imports from the NXT:1970i and less advanced bucket, and from the NXT:1980i bucket beginning in 2018. This allocation is an accounting convention that reflects our modeling of China’s purchases during these periods rather than an independent estimate of the scanner mix at multinational fabs.

Installations at key fabs

We estimate installations at key fabs involved in AI chip production, using public shipment records and reporting. We examine three firms in depth: SMIC, China’s flagship logic foundry; CXMT, China’s flagship HBM maker; and YMTC, China’s flagship NAND maker. YMTC is relevant because it is a major purchaser of advanced lithography systems; understanding its fleet helps bound how many of the most advanced NXT:2050i/2100i systems remain available to logic and DRAM producers.

CXMT

We estimate NXT:2100i and NXT:2050i installations by cross-referencing shipments reported by the Select Committee (Table 38) with a 2025 presentation from Jiufu Technology Group (Table 40), a contractor that supplies lithography scanner foundations. Jiufu reports delivering 2 foundations classified as NXT:2100i to CXMT Beijing and 7 NXT:2100i foundations to CXMT Hefei. However, the Select Committee reports that only six NXT:2100i systems have entered China in total. The most likely explanation is that the foundations reported by Jiufu can be used for either NXT:2050i or NXT:2100i. We treat the nine foundations as supporting six NXT:2100i and three NXT:2050i, with uncertainty over allocation between Hefei and Beijing.

For NXT:1980i, Jiufu reports 12 delivered foundations at Hefei, 8 delivered foundations at Beijing, and 13 outstanding Hefei orders (without specifying the model). We set:

• Hefei P50 at 25, equal to 12 delivered orders plus the 13 outstanding orders, assuming all of these became NXT:1980i deliveries. This estimate is supported by Anhui imports and the capex cross-check below. P10 is set at 12, allowing for the possibility that none of the orders were NXT:1980i. P90 is set at 33, consistent with the upper end of the customs-based estimate.
• Beijing P50 at 8, equal to Jiufu’s reported foundation deliveries. We set P90 at 11 to allow for additional deliveries since the 2025 presentation and P10 at six in case some foundations are used for other NXT systems.

As a cross-check, we independently estimate NXT:1980i based on CXMT’s $32.2 billion capex on gross machinery and equipment as of 2025 (Table 39). First, we assume that ~90% of CXMT’s machinery is front-end wafer fabrication equipment (WFE).^{Sidenote 139} Second, we estimate that lithography accounts for approximately 19% of China’s WFE spending.^{Sidenote 140} Multiplying the factors, we estimate that lithography accounts for ~17% of CXMT’s machinery capex. Next, we estimate that immersion accounts for 75% of this capital, which matches ArFi’s share of ASML’s DUV scanner revenue. Applying this share to CXMT’s estimated capex implies $4.1 billion of capital on DUVi systems.

From the DUVi capital stock, we subtract nine reported NXT:2050i/2100i systems at $90 million each, allocate 5% for installation and capitalized upgrades, and assume 95% of the remainder corresponds to NXT:1980i rather than predecessors. Dividing by NXT:1980i’s $76 million ASP, we estimate 39 NXT:1980i systems, a close match to the estimate from the Jiufu presentation.

One overarching uncertainty is whether CXMT continues to receive NXT:1980i systems to this day. The Dutch government requires a license for these systems nationwide, but the Select Committee’s data confirm that they continue to enter the country. The Anhui customs data provides some evidence that CXMT has been able to obtain NXT:1980i systems in recent years.^{Sidenote 141}

SMIC

We estimate that SMIC has 6 / 7 / 8 NXT:2050i systems at SMIC South in Shanghai, based on the following.

1. The Select Committee on the CCP reports that ASML sold 22 NXT:2050i systems to China during 2021–2023 and none in 2024. Public reporting indicates that two of these were delivered to SMIC South in 2021.
2. A September 2023 equipment ledger reproduced on the Sino Defence Forum reported four NXT:2050i systems at SMIC South—two delivered in 2021 and two in June 2023—and the accompanying discussion identified another three systems scheduled for delivery by year-end.
3. A later Sigmaintell report stated that SMIC acquired three NXT:2050i systems in 2024. Because the Dutch government reportedly began denying licenses for NXT:2050i beginning January 2024, we interpret these as systems imported in late 2023 but installed in 2024.

We estimate SMIC’s NXT:1980i fleet drawing from a September 2023 SemiAnalysis report claiming that SMIC already possessed “well over 30” advanced ASML ArFi systems and had ordered additional NXT:1980i systems. SemiAnalysis also estimated that SMIC’s first 7nm fab would contain 15 ArFi systems when fully equipped by the end of the second quarter of 2024. We translate this into approximately 30 / 36 / 42 total ArFi systems in September 2023, rising to 31 / 40 / 48 after allowing for tools already ordered or undergoing installation before January 2024, and subtract the estimated NXT:2050i systems above.

The main uncertainty is whether SMIC continued to receive NXT:1980i systems after 2023. SMIC’s principal Beijing and Shanghai entities—including SMIC Beijing, SMIC North, SMIC Shanghai and SMIC South—are designated with Footnote 5 on the US Entity List and barred from receiving NXT:1980i by US rules. However, although the Netherlands has required a license for NXT:1980i, the Dutch government does not publicly disclose its licensing decisions for individual customers or fabs. Our estimate assumes that SMIC’s Beijing and Shanghai fabs have not obtained additional NXT:1980i systems from 2024 onward. If the Netherlands have granted further licenses, the installed base will be higher.

The geographic allocation is less certain. The same Sino Defence Forum equipment ledger identified six NXT:1980i systems at SMIC Beijing and six at SMIC South, alongside five purported NXT:2000i systems at SMIC South. We use six Beijing systems as the lower estimate and assume the rest of the remaining fleet is allocated to Shanghai, where SMIC’s advanced production is concentrated.

YMTC

We estimate that YMTC has 5/7/9 NXT:2050i systems, based on five considerations:

1. Supportive (though limited) direct evidence. A February 2022 industry-forum post claims that YMTC had obtained NXT:2050i systems, and contemporaneous Chinese reporting identifies ASML as a major supplier.
2. The national allocation of NXT:2050i systems. We estimate that China imported 22 NXT:2050i in total, with 6 / 7 / 8 estimated for SMIC, three for CXMT, and one for Hua Hong. This leaves 11 unaccounted for.
3. YMTC’s status as a major purchaser of WFE, at a scale comparable to SMIC and CXMT. YMTC’s gross machinery capital at year-end 2023, excluding Wuhan XMC, was RMB120 billion, 25% greater than CXMT’s and 60% as large as SMIC’s.
4. The timing of YMTC’s capacity expansion. Fab 1 ramped during 2021 and Fab 2 ramped during 2022–2023, closely matching the period during which China imported NXT:2050i.
5. YMTC’s manufacturing scale. Fab 1 reached 100,000 wafer starts per month (WSPM), close to the 120,000 WSPM scale of CXMT’s Phase I project, for which we estimate CXMT acquired 9 NXT:2100i and NXT:2050i systems.

In sum, YMTC’s scale and the timing of its expansion make it the leading candidate for bulk purchases of NXT:2050i in the relevant period. We estimate it acquired the majority of the 11 remaining systems, matching the scale of SMIC and CXMT, with P10 and P90 bounds to reflect uncertainty as to the specifics of its purchases.

Multinational fabs

We estimate imports at four known multinational fabs operating within China: Samsung Xi’an (Shaanxi province), SK hynix (formerly Intel) Dalian (Liaoning province), and SK hynix Wuxi and TSMC Nanjing (both Jiangsu province). For 2015–2026Q1, we use the customs model above to isolate imports to these provinces, which are a plausible upper bound on imports to the relevant fabs. We do not attempt to identify system models.

We assign all inferred Shaanxi and Liaoning immersion imports to the multinational fabs, because of an absence of evidence of other plausible DUVi purchasers in those provinces. Jiangsu has several fabs plausibly capable of receiving DUVi systems, including Hua Hong’s Fab 7 and Rong Semiconductor’s Huai’an line. We set Jiangsu’s multinational fab share at 70/85/100%, which is drawn once per simulation and shared across years.

For 2012–2014, before the customs series begins, we estimate 4 / 6 / 8 systems at SK hynix Wuxi and 1 / 3 / 6 systems at Samsung Xi’an. Together, these represent roughly half of the period’s estimated 12 / 15 / 20 national imports. We allocate more to Wuxi because it was already producing 29nm DRAM, for which DUVi is used, while Samsung Xi’an began production only in 2014. Both estimates are capped at the national estimate, based on ASML financial data, within each draw. We did not find evidence that the other two fabs ramped during this time period.

We obtain an estimate of 42 / 52 / 67 systems across fabs.

Other known installations

Public sources identify several additional installations beyond SMIC, CXMT, and YMTC. These are not estimates of the entities’ complete installed bases and should not be summed across sources. Notably, some of the sites listed by Jiufu are anonymous and might therefore overlap with previously discussed SMIC/CXMT fabs or the separate Hua Hong observation. The allocation in the summary table assumes these observations are distinct; any overlaps would increase the unallocated NXT:1980i residual.

Allocation to advanced fabs

Building on the estimates above, we estimate the fraction of China’s DUVi stockpile that is installed within fabs producing advanced logic or DRAM suitable for AI chips. These estimates are highly uncertain, especially for NXT:1980i, because of uncertainties regarding (i) the total number and locations of China’s advanced fabs and (ii) the implementation of Dutch licensing policy on exports to these fabs.

For NXT:2050i and NXT:2100i, we use the allocations estimated above: 5 / 7 / 9 NXT:2050i systems at YMTC (assumed to be used for NAND production and excluded from the totals above), six NXT:2100i and three NXT:2050i at CXMT, 6 / 7 / 8 NXT:2050i at SMIC, and one NXT:2050i at Hua Hong Fab 6. This leaves an estimated 2 / 4 / 6 NXT:2050i unaccounted for. We assume that these systems are located at advanced fabs, rather than legacy fabs, because they (i) are unnecessary for legacy production, (ii) cost more than earlier systems that enable legacy production, and (iii) were primarily imported in 2023, when Chinese buyers anticipated impending countrywide restrictions. We assume an even split between logic and DRAM.

For NXT:1980i, no comparable fab-level allocation exists. We estimate the advanced-node fleet by running a Monte Carlo simulation over five components:

• SMIC’s Shanghai fabs (19 / 24 / 28) and CXMT (20 / 33 / 44), based on the estimates above. We exclude SMIC Beijing’s 6 / 9 / 12 systems, because these fabs are believed to produce only at legacy nodes.
• Guangdong advanced fabs (3 / 6 / 22). Several Huawei-linked fabs are located in Guangdong, including PXW, a rumored 7nm facility in Shenzhen, and SwaySure’s DRAM lines. Guangdong’s estimated NXT:1980i-priced imports (32 / 41 / 54) provide an upper bound on the installed base at these facilities; subtracting the 10 NXT:1980i foundations that Jiufu reported as delivered to PST Shenzhen—a legacy logic (40nm / 28nm) fab—leaves 22 / 31 / 44. There is further uncertainty as to how many systems were obtained by SMIC’s 28nm Shenzhen fab, how many of PST Shenzhen’s remaining 17 orders were NXT:1980i, and what other legacy facilities might have received orders.
• Shanghai’s advanced logic fabs other than SMIC (5 / 19 / 49). Shanghai’s estimated NXT:1980i-priced imports total 77 / 97 / 127. We attribute 19 / 24 / 28 to SMIC Shanghai. Subtracting the central estimate of 24 leaves 53 / 73 / 103), including advanced facilities like Hua Hong’s Fab 6 (reported to hold at least one NXT:1980i, one NXT:2050i, and four unidentified DUVi) and Fab 8a, which is reported to have a 7nm line. This total also includes imports to legacy fabs such as SMIC Lingang and Hua Hong’s 300mm Fab 5. We use a wide P90 to reflect the uncertainty in the division of these tools between advanced and legacy fabs.
• Beijing’s advanced fabs other than SMIC and CXMT (1 / 2 / 22). Beijing’s estimated imports total 50 / 63 / 81. Subtracting the SMIC Beijing and CXMT Beijing allocations within draws leaves 32 / 46 / 64. We are not aware of other Beijing fabs with advanced logic or DRAM production, and it is possible that these systems all went to legacy fabs (e.g., SMIC Jingcheng) but there is still substantial uncertainty. We estimate a low median but leave significant upside uncertainty, reflected in the P90.
• Advanced fabs in other provinces (1 / 3 / 30). The only documented candidate is JHICC in Fujian, a DRAM fab reportedly participating in Huawei’s HBM consortium. Collectively, provinces not listed in Table 28 imported an estimated 34 / 43 / 57 systems, including a 2024 spike of 17 / 22 / 29. Our P90 allows for the possibility that most of this spike went to advanced fabs not known to the authors.

Data sources

Appendix F: Lithography-bounded Chinese AI chipmaking

This appendix compares projected AI chip production in the US and allied ecosystem through 2035 with bounds on Chinese production imposed by limitations on access to DUVi lithography systems. For China, we model production as bounded by its existing ASML scanner stockpile, potential future ASML imports, and indigenously produced scanners. We evaluate five import environments: imports banned beginning in 2027, imports continuing at the 2024–2025 pace, and modeled “Diminished”, “Robust”, and “Acceleration” trajectories. We also model three allocations of DUVi systems within China: a “Baseline” that maintains the current split of China’s DUVi system fleet between advanced and legacy fabs; a “Mobilization” in which China achieves the allocation found in the US and allied ecosystem; and a “Physical Ceiling” that assigns every usable scanner to AI production.

The China estimate assumes that every complementary chipmaking bottleneck—including etch, deposition, metrology, HBM stacking, and advanced packaging—is eliminated, leaving lithography as the sole constraint. The resulting estimates are therefore lithographic capacity bounds rather than forecasts of realized production. These bounds are unrealistic in the near term, given China faces numerous additional constraints, but they reveal the production capacity enabled by varying policy choices. Additionally, they may become informative in the mid term if China indigenizes complementary SME bottlenecks.

China estimates are reported as P10 / P50 / P90 quantiles from 100,000 Monte Carlo draws, conditional on each import and allocation scenario. US and allied estimates are low, central, and high forecasts. All production figures are reported in millions of H100-equivalents.

We find:

1. Banning new DUVi system exports ensures a large US and allied advantage in AI chipmaking through 2035. Even under extreme assumptions, in which China: (1) mobilizes 100% of its in-country DUVi systems for AI chip production, violating existing export controls; reaches world-class yields and throughputs by 2031, (2) indigenizes every complementary tool required for AI chipmaking, and (3) indigenizes DUVi systems capable of NXT:1980i in 2030 (much earlier than our median estimate) and scales up indigenous DUVi system production at an unprecedented rate of 100% year over year, we estimate China’s installed DUVi systems will support a maximum of 87 / 153 / 321 million H100-equivalents annually by 2035, of which 66 / 112 / 224 million comes from the ASML stockpile as of 2026Q1, 13 / 21 / 42 million from systems estimated to be imported during 2026Q2–Q4, and 8 / 20 / 55 million from indigenously produced DUVi systems. In the same year, US and allied production is estimated at 422 / 974 / 3,566 million in 2035. China’s P50 estimate is 16% of the US central case.
2. Continued NXT:1980i imports could erode—and under some assumptions eliminate—the US chipmaking advantage. If imports continue at the 2024–2025 pace, China could reach 166 / 309 / 642 million H100-eq if mobilized for AI production and 249 / 434 / 877 million at the Physical Ceiling, by 2035. Assuming a moderate increase in imports over time (the “Robust” scenario), these rise to 204 / 378 / 784 million under Mobilization and 306 / 532 / 1071 million at the physical ceiling. These medians would still trail the US median estimate (974 million) but could surpass the low estimate.

US ecosystem production model

We estimate annual AI chip production available to the US and allied ecosystem, in millions of H100-equivalents, using market forecasts through 2028 and an average of a demand projection and a lithography model for 2029 to 2035.

For 2026 and 2027, we use estimates from TrendForce of 13.9 and 29.3 million GB300-equivalents, corresponding to ~35 million and ~74 million H100-equivalents using dense FP16 throughput, with 10% uncertainty for P10 and P90. For 2028, we use AI 2040’s forecast of US compute addition growth of ~99% relative to 2027^{Sidenote 145} and add 20% uncertainty.

For 2029–2035, we average a demand forecast with an estimate of AI production supported by available EUV capacity. We estimate demand growth at [16 / 32 / 56] percent, as the product of chip revenue growth and growth in H100-eq per revenue dollar.

The P50 is anchored to hyperscaler capex growth over 2018–24, reflecting the assumption that chip spending growth returns to the long-run trend for cloud and AI infrastructure after a fast growth period in the 2020s. Capital expenditure at Alphabet, Microsoft, and Meta increased from $50.7 billion to $136.2 billion, implying a 17.9% CAGR. Including Amazon increases this to 22.9%, but includes substantial fulfillment infrastructure. We use a rounded 20%. For yearly improvements to H100-equivalents per dollar, we take AI 2040’s forecast that by 2028, compute cost-efficiency growth will have slowed to 10% compared to 25% across 2025–2028 and 40% before that. The P10 assumes 10% revenue growth, close to ASML’s 9% semiconductor-market outlook. The P90 assumes 30%, representing continued exceptional expansion. Its 20% yearly improvement in H100-eq per dollar is deliberately optimistic, to capture advances in architecture and performance. The resulting unconstrained demand estimates are:

The EUV model separately estimates gross EUV supply and the residual capacity available for AI after non-AI production, and depends on fleet size, scanner productivity, H100-eq per exposure, and competing non-AI demand.

• EUV fleet size. We estimate approximately 310 installed low-NA EUV systems at the start of 2026. ASML’s guidance implies 65 shipments in 2026, a 30% increase to 85 in 2027; it is investigating a further 30% increase, to roughly 110, in 2028. After 2028, P10 holds additions at 110 systems annually; P50 and P90 respectively increase by 10% and 30% year over year after 2028. Scanners delivered during a year receive half weight, approximating an evenly distributed delivery schedule.
• EUV exposure throughput. Following SemiAnalysis, we assume that an EUV averages 75 wafer-exposures per hour at 90% uptime, corresponding to ~590,000 exposures per year. We assume that scanner productivity increases by 0% / 1.5% / 3% annually. The central assumption is conservative relative to marketed improvements to reflect the fact that fleet-average performances improve more slowly as older scanners remain in use. We assume H100-eq per exposure improves at 1% / 3% / 8% annually, capturing net improvements in performance per unit of lithographic capacity.
• Non-AI EUV demand. We estimate this at ~159 million exposures in 2026 (based on 35 million H100-eq, 1.05 exposures per H100-eq, and an estimated fleet size of (310+375)/2 = 342 scanners). We assume non-AI demand grows at 6% / 9% / 12% annually. The P50 is anchored on the ASML 9% outlook, while P10 and P90 add uncertainty.

China ecosystem production capacity model

We model China’s lithography-bounded AI chip production capacity under five import environments and three allocation scenarios:

• Import environments. All five environments include an estimated 69 systems imported during 2026 but add only the 56 / 58 / 60 systems estimated after the existing stockpile measurement at the end of Q1. “Imports banned” sets imports to zero beginning in 2027. “2024–2025 Pace” fixes imports at 90 systems annually, matching the 2024–2025 pace of imports. “Diminished” assumes that China’s imports pull back from the recent pace. “Robust” assumes healthy but not extreme growth from the 2024–2025 baseline. “Acceleration” assumes an extreme expansion in global lithography capacity, extending ASML’s announced 30% capacity ramp indefinitely, while maintaining China’s 2024–2025 share of imports. These scenarios are described at greater length, below.
• Allocation scenarios. “Baseline” broadly continues the present allocation, as shaped by commercial incentives, Dutch licensing policy, and export control effectiveness. “Mobilization” assumes China reorganizes lithography capacity towards AI production, including potentially by circumventing export controls. “Physical Ceiling” assigns every usable scanner to AI chip production, estimating the upper bound enabled by China’s in-country DUVi systems.

The following table reports P10 / P50 / P90 annual output for every combination of scenarios. Contributions from indigenous production and the existing stockpile are Shapley-attributed within the “Robust” import environment; they can vary across import environments because additional scanners may relieve a logic or DRAM bottleneck and thereby change the marginal value of other scanners. The final column sums production from all three sources under the “Robust” import scenario.

China’s annual AI chip production for a given year is modeled as:

where:

• Physical chip throughput is the rate at which each scanner enables production of complete chip packages, incorporating scanner exposure throughput, lithography passes per wafer, dies per wafer, frontend die yield, HBM stacking yield, and packaging yield. It is calibrated using the Ascend 910C, as a stand-in for a reference chip with a comparable fabrication footprint. We sample 2026 throughputs of NXT:1980i and NXT:2050i/2100i systems from the SMIC / CXMT distributions in Appendix D, then increase them smoothly to the mature levels (TSMC / SK hynix) by 2031. Where the fleet is inefficiently allocated between logic and memory, output is limited by the smaller capacity.
• Performance per chip captures computing power, modeled in H100-equivalents, provided by the reference chip package. It captures performance improvements that are independent of lithographic capability (e.g., better chip architecture). We model it as a 1% / 3% / 8% annual increase, matching the US production model’s factor.

The implementation separately models NXT:1980i and NXT:2050i/2100i scanners, and separately tracks logic and HBM. The multiplicative expression above is a conceptual simplification.

Existing Stockpile

China’s existing DUVi system stockpile is estimated in Appendix E as 249 / 270 / 294 NXT:1980i systems, 22 NXT:2050i systems, and six NXT:2100i systems, imported by Chinese-owned fabs through 2026Q1. We exclude NXT:1970i and less advanced systems, which we have not established as capable of making advanced logic and HBM. This assumption does not meaningfully affect our top-line conclusions, as these systems are a minority of China’s installed base and are less capable than the scanners included in the model.

Indigenous production

Indigenous production is modeled using two independently sampled factors.

• Commercial-equivalence year: the first year in which China produces a commercially viable scanner capable of matching NXT:1980i’s performance for advanced AI chip production, modeled at 2030 / 2033 / 2036. The P50 reflects the extrapolations from ASML’s history and China’s past progress described in Section 3, while leaning to the earlier end of the plausible range. P10 allows for faster progress, potentially enabled by massive state investment. P90 allows for some technical challenges to remain intractable for substantially longer.
• Production ramp: production begins at five systems, doubles to 10 and 20 in the next two years (reflecting rapid scale-up from a very low initial base), and then grows at 30% / 50% / 100% annually. The 30% case resembles ASML’s announced near-term capacity expansions; the 50% case is an exceptionally fast but historically grounded ramp (a CSET review of the industry’s longer history separately estimated that 60% annual growth had been achieved only twice in the lithography industry’s history: first at Nikon and later at ASML); the 100% assumes unprecedented mobilization.

New Imports

We model five import scenarios. All scenarios assume China imports 69 systems during 2026, the midpoint between an extrapolation of its 2026Q1 pace and the 2024–2025 pace.

We anchor near-term estimates to (i) China’s roughly 90 NXT:1980i imports over 2024–2025 and (ii) ASML’s planned immersion capacity expansions: 130 systems in 2026, a 30% expansion in 2027, and a potential 30% expansion in 2028, to roughly 220 systems. The 2028 estimates correspond to China receiving 25% / 40% / 70% of that output. The “Diminished” scenario settles slightly above China’s pre-2023 share, “Robust” is near the midpoint between its pre- and post-2023 shares, and “Acceleration” preserves its approximately 70% share over 2024–2025.

After 2028, we model imports as a function of two factors:

• Growth in worldwide DUVi system shipments (0% / 10% / 30%), matching EUV growth estimated in the US production model. “Robust” is anchored to 10% growth, consistent with ASML’s projection that DUV wafer exposures will rise from ~525 million in 2024 to 900 million in 2030. “Diminished” assumes the 2026-28 expansion is followed by a flat cycle, with growing exposure demand absorbed by the enlarged installed base. “Acceleration” mechanically extends ASML’s announced capacity ramp through 2035. The resulting scale is extreme, but useful for contemplating the consequences if ASML’s near-term expansion becomes a sustained trend.
• China’s share of worldwide DUVi system shipments (25% / 40% / 70%). “Diminished” settles slightly above its pre-2023 share. “Acceleration” assumes China maintains the 2024–2025 share. “Robust” assumes the share settles near the midpoint between the pre- and post-2023 imports.

Imports receive half weight in their delivery year, reflecting evenly distributed arrivals, and full weight thereafter.

AI Allocation

We model three scenarios for allocation of DUVi systems to advanced-node AI production.

Current allocations are estimated as follows:

• Allocation to advanced fabs. We adopt the estimates from Appendix E. Advanced logic is estimated at 37 / 57 / 89 NXT:1980i systems and 9 / 10 / 11 NXT:2050i systems. Advanced DRAM is estimated at 29 / 44 / 62 NXT:1980i, 4 / 5 / 6 NXT:2050i, and 6 NXT:2100i. Accounting for joint uncertainty, 27% / 38% / 53% of the Chinese-owned NXT:1980i fleet is located at advanced logic or DRAM fabs.
• Allocation of advanced-fab scanners to AI. We estimate that 5% / 10% / 20% of advanced lithography capacity is devoted to AI chips. For logic, Epoch estimates that Huawei will produce around 1 million Ascend 950 packages in 2026, each containing two compute dies of approximately 400 mm². A 300mm wafer holds roughly 140 dies of that size. Assuming 30–50% die yield, this would require 2,500–4,200 wafers per month, roughly 4–7% of SemiAnalysis’s estimated SMIC’s advanced-node capacity at 60,000 wafer starts per month. Epoch also projects 430,000 Ascend 910Cs, but some may use foreign dies fabricated at TSMC. Accounting for production by other Chinese AI chip designers, potential domestic 910C production, and uncertainty in output and yields supports a wider 5–20% range. For memory, Epoch estimates CXMT’s 2026 HBM allocation at 30,000 wafer starts per month by the end of 2026. This comes out of roughly 350,000 total DRAM wafer starts per month. Assuming advanced nodes constitute between one-half and all of CXMT’s capacity, the implied advanced-node share for HBM is 9–17%.

For later years, the allocation varies by scenario:

• Baseline assumes continuity with the present allocation, as influenced by commercial and policy factors. As discussed in Section 5, the Dutch government requires a license for exports of NXT:1970i and NXT:1980i within China. There is substantial uncertainty regarding which licenses are currently being granted and, more broadly, how effectively the broader control structure can prevent diversion, diversion in place, and other tactics that China might use to obtain NXT:1980i at fabs making AI chips. As discussed in Appendix E, there is evidence that NXT:1980i systems have reached advanced fabs, such as CXMT and Hua Hong. Rather than making assumptions about Dutch licensing policy or the effectiveness of enforcement, Baseline assumes that approximately the present mixture of policy impact and commercial incentive persists into the future: existing tools remain at their estimated fab types (Appendix E), while imported and indigenous systems enter advanced fabs in the same proportion (27% / 38% / 53%) as the current fleet. Within those advanced fabs, AI allocation rises smoothly from 5% / 10% / 20% to the outside-China allocation (see US production model, above) by 2030, then tracks it through 2035.
• Mobilization assumes that Chinese fabs strongly prioritize AI production and find ways to circumvent any future policies that suppress the current allocation at advanced fabs—whether through overt violation, illicit diversion, misleading end-use claims, diversion in place, or other sophisticated evasion. We use the single allocation factor estimated in the US production model above, tracking the share of the fleet devoted to AI production.
• Physical ceiling allocates the entire existing stockpile and every imported or produced system to advanced fabs.

In the “Mobilization” and “Physical Ceiling” scenarios, we allow DUVi systems to be divided between logic and DRAM to maximize Ascend 910C output, reflecting strong prioritization of AI output. The “Baseline” scenario assumes the existing logic/DRAM split of currently installed DUVi systems.

Caveats

• The China estimates are AI chip production upper bounds based on aggregate DUVi system capacity, not forecasts of actual AI chip production. Full utilization of China’s DUVi installed base could be bottlenecked by lack of etch, deposition, metrology, advanced packaging, and HBM fabrication and stacking tools, as well as masks, servicing, skilled labor, power, and demand.
• The model assumes no scanner retirements, failures, re-exports, or servicing losses. This may overstate usable capacity later in the forecast and means that a ban on servicing would probably constrain China more than the modeled import ban alone.
• The model assumes that ASML continues producing China-eligible NXT:1980i systems rather than retiring it in favor of the most advanced DUVi systems (i.e. the NXT:2000i and more advanced), which cannot be sold to China.
• The model assumes that Chinese fabs reach mature TSMC and SK hynix AI chip yield and throughput by 2031. This requires China to rapidly improve process control, HBM stacking, and advanced packaging.
• The “Mobilization” and “Physical Ceiling” scenarios assume widespread diversion in violation of US export controls and an ideal balancing of DUVi systems across logic and HBM fabs. They do not model fab construction time, process qualification time, downtime, or the opportunity cost of reducing legacy and non-AI chip production, all of which could reduce Chinese AI chip output.
• The DUVi system indigenization and scale-up estimates are highly speculative, relying on uncertain estimates of when China achieves commercially viable DUVi systems and how quickly Chinese DUVi providers can scale commercial production.
• The model’s US production forecast depends on an average of a demand model and a model of EUV supply for AI chipmaking. It does not separately constrain HBM, advanced packaging, substrates, power, data-center construction, DUVi machines for certain layers, or High-NA EUV.

Authors

Nicholas Brown is a Senior Fellow at the Center for Technology & Statecraft. Saif M. Khan is Director of the Center for Technology & Statecraft.

Acknowledgements

For helpful discussions, comments, and input, we thank Cynthia Light Brown, Jack Freed, Joseph Fridman, Jimmy Goodrich, Lennart Heim, Jeremy Lansford, Hamish Low, Mary Clare McMahon, Amelia Michael, Konstantin Pilz, and James Sanders. The authors are solely responsible for all mistakes.